Hi, In the ug230.pdf (user guide for Spartan-3E Starter Kit) page.76, figure 10-4 the timing caracteristics of the SPI interface of the LTC6912-1 pre-amplifier are the following: - SPI_SCK LOW=50ns - SPI_SCK HIGH=50ns - AMP_CS LOW to SPI_SCK=30ns - SPI_MOSI VALID to SPI_SCK SETUP=30ns - AMP_DOUT OUTPUT DELAY=85ns
When I look at the schematics of the ADC/DAC part of the board (ug230.pdf, p.151) I see than V+=3.3V and V-=0V for the pre-amplifier.
I took a look at the LTC6912-1 datasheet (got from the link on page 79 in ug230.pdf) and on page 11 in the section "SERIAL INTERFACE SPECIFICATION" I see that for V+=2.7V~4.5V the following timing parameters should be used: - CLK (== SPI_SCK) LOW=100ns - CLK (== SPI_SCK) HIGH=100ns - CS/LD (==AMP_CS) LOW to CLK (== SPI_SCK)=30ns - DIN VALID to CLK (== SPI_SCK) SETUP=60ns - DOUT (== AMP_DOUT) OUTPUT DELAY=125ns
Can anyone (preferably from Xilinx) explain me if it's some miscomprehension from me or if there is some error in the documentation and if so than please tell me which parameters should I take into consideration.
Best Regards Mehdi TAILEB