Field-Programmable Gate Arrays

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ChipScope - impact on design or not?

I used to believe that ChipScope did not have any impact on the design. I used to. I have two FPGAs communicating on th...
17 comments posted 19yrs
posted by xjohbex
17 comments posted 19yrs posted by xjohbex

remove logic redundancy

Hello, I'm developing a redundant design in ISE of Xilinx. When I simulate a design the tool shows the following messag...
7 comments posted 19yrs
posted by hsfranck
7 comments posted 19yrs posted by hsfranck

ethernet checksum nightmare

Hi, I have been fighting with this for some time now and I cannot figure it out. I have read the 802.3 information and...
14 comments posted 19yrs
posted by axr0284
14 comments posted 19yrs posted by axr0284

Why AHDL didn't catch on like Verilog or VHDL?

Hello, I've been using AHDL for a while and the people in my shop have been using it since it was developed. I think it...
2 comments posted 19yrs
posted by jjlindula
2 comments posted 19yrs posted by jjlindula

assigned a special pins in ISE

Where I may assigned a special pins: Rocket IO Rx and Tx ?
3 comments posted 19yrs
posted by axalay
3 comments posted 19yrs posted by axalay

SystemVerilog Sequence Coverage Problem?

Hi all, I am reading some FIFO code by SystemVerilog. But there is a part of code confused me. It seems to count push a...
0 comments posted 19yrs
posted by zhushenli
0 comments posted 19yrs posted by zhushenli

Problem in Xilkernel

I have a problem when I try to use Xilkernel in a Spartan 3E. I initialize the "xilkernel_main()", and all seems to be...
2 comments posted 19yrs
posted by pbantunez
2 comments posted 19yrs posted by pbantunez

Impact with non-standard LPT base addresses

set XIL_IMPACT_ENV_LPT_BASE_ADDRESS=D880 set XIL_IMPACT_ENV_LPT_ECP_ADDRESS=D800 like this, works! until that I was very...
3 comments posted 19yrs
posted by antti
3 comments posted 19yrs posted by antti

moving from xlinx 8.1 to 8.2 or better wait ?

We got most of recent designs done in the former xlinx version 8.1 and consider continuing with the most recent version...
6 comments posted 19yrs
posted by fpgaengineerfrankfurt
6 comments posted 19yrs posted by fpgaengineerfrankfurt

better ways for debugging?

hi all, im in the process of designing and implementing a digital system on a spartan 3 FPGA. apart from the FPGA, im u...
8 comments posted 19yrs
posted by manusha
8 comments posted 19yrs posted by manusha

Judge complex degree by state numbers?

Hi, I have met some situations that people evaluate a design's complex degree by asking "How many states does the state...
4 comments posted 19yrs
posted by topweaver
4 comments posted 19yrs posted by topweaver

OPB master implementation

Hi, I am designing an OPB Peripheral which has to act as a master and a slave on the OPB Bus . I am not happy with the...
4 comments posted 19yrs
posted by get2venu
4 comments posted 19yrs posted by get2venu

Need Recommandation for DDR2 controller virtex4

Hello all, I am trying a new design that includes DDR2. This design has multiple accses to the memory and I need to use...
3 comments posted 19yrs
posted by guybye
3 comments posted 19yrs posted by guybye

mobius, from codetronix, anyone has been tested

Hello, I'am looking for a software to efficiently implement FPGA designs, or target to embeded processor, - simpler, -...
1 comments posted 19yrs
posted by someone
1 comments posted 19yrs posted by someone