Field-Programmable Gate Arrays

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Matlab (.m) to VHDL

Hello, I have seen this question many times in the newsgroups but I did not see a clear answer. I have to perform vario...
3 comments posted 19yrs
posted by m.vitaliy
3 comments posted 19yrs posted by m.vitaliy

max II dev kit pin grid

hi just done the vending machine demo, is there a pin grid to specify the output somewhere i've missed, or does aal thi...
0 comments posted 19yrs
posted by jackokring
0 comments posted 19yrs posted by jackokring

IEEE fixed-point package FATAL_ERROR

Hello, Just started recently playing with a VHDL-1993 compatible fixed-point package: http://www.vhdl.org/vhdl-200x/vhd...
0 comments posted 19yrs
posted by mloulah
0 comments posted 19yrs posted by mloulah

Help with xilinx simulation?

Hello all, I am using xilinx ISE 8.2i , my program is as follows, entity mod1 is Port ( a : in STD_LOGIC; y : out STD_LO...
10 comments posted 19yrs
posted by <xx>
10 comments posted 19yrs posted by <xx>

FSL feasibiliity

Hi, Can anyone tell me the fastest interface from Microblaze and PowerPC to a custom peripheral if it were to be used f...
1 comments posted 19yrs
posted by hattangady
1 comments posted 19yrs posted by hattangady

DCM start up

I've got a DCM as part of a 4 byte Aurora implementation on a VII Pro. Sometimes after JTAG configuration the DCM just...
4 comments posted 19yrs
posted by enquiries
4 comments posted 19yrs posted by enquiries

What next next big thing coming for HDL?

Hello, I''ve been talking with a co-worker about the HDL languages that are availabile these days, such as VHDL, Verilo...
9 comments posted 19yrs
posted by jjlindula
9 comments posted 19yrs posted by jjlindula

How to simulate from the xilinx ISE

Hello all, How do I start a simulation from the xilinx ISE? thanks.
2 comments posted 19yrs
posted by <phooey>
2 comments posted 19yrs posted by <phooey>

XILKERNEL and MICROBLAZE (how to probe this)

Has somebody tried to config Xilkernel with the XPS. I have a Spartan 3E and XPS 8.1, and I've added Xilkernel with an...
1 comments posted 19yrs
posted by pbantunez
1 comments posted 19yrs posted by pbantunez

Embedded Development Tools

Hello, Here is our web site www.ezEmbedded.com for your reference and I am very happy to assist you on your project. Pl...
1 comments posted 19yrs
posted by ezembedded
1 comments posted 19yrs posted by ezembedded

timing?

Hi all, I have the following question, this is my program, `timescale 1ns / 1ps module oscdiv10(in,out); input in; outp...
3 comments posted 19yrs
posted by <223>
3 comments posted 19yrs posted by <223>

Soft processor Microblaze vs embedded core PowerPC

Hi, I am unable to come across any material that critically examines the reasons I must go in for Microblaze or Powerpc...
4 comments posted 19yrs
posted by hattangady
4 comments posted 19yrs posted by hattangady

New user help required

Hello, I am starting with fpga and I have some questions, My first question is do I need a clock input? I want to build...
4 comments posted 19yrs
posted by khal
4 comments posted 19yrs posted by khal

Manually creating a LUT in VHDL

Does anyone know if it is possible to define the values in a lookup table using VHDL compatible with Xilinx tools? If so...
4 comments posted 19yrs
posted by dpmontminy
4 comments posted 19yrs posted by dpmontminy