Hi, I have been fighting with this for some time now and I cannot figure it out. I have read the 802.3 information and I have read a lot of forums and they all have some kind of general answer.
I am trying to create a very simple MAC module that will send data to a PHY for transmission. I am currently using the aesic crc VHDL function to perform my CRC checks.
Let's say I want to send the following packet (I know this is not a correct ethernet packet. Bear with me):
00 00 12 33 FF FF (in bytes) The bytes will be sent with the left most byte first.0000 0000 0000 0000 0001 0010 0011 0011 1111 1111 (in bits)
I would first switch the bits in each byte individually and then feed it to the CRC module which has been initialized with all 1s.
Therefore
0000 0000 0000 0000 1000 0100 1100 1100 1111 1111is fed into the CRC module starting with the byte on the left most side.
Hopefully this is correct so far.
After the last byte is fed through, I will grab the output of the CRC module, Invert it and shift it's bits.
The output from the CRC is
7E 11 64 34 ( in bytes)0111 1110 0001 0001 0110 0100 0011 0100 ( in bits)
After inverting
1000 0001 1110 1110 1001 1011 1100 1011 ( in bits)After switching
1101 0011 1101 1001 0111 0111 1000 0001 ( in bits)D3 D9 77 81 ( in bytes)
This means that my packet that I will send to the PHY will be start with the left most byte
00 00 12 33 FF FF D3 D9 77 81 ( in bytes)This value seems to agree with some CRC32 software I found on the net.
**************************************************NOW lets say i am receiving this data from the PHY.
00 00 12 33 FF FF D3 D9 77 81 ( in bytes)I do the same as for sending, I switch the bits in each byte (including the FCS) and feed it to the CRC module which has been initialized to all 1. After sending the right most byte, I should get the magic number C7 04 DD 7B out which says that it is working but i don't. Below is the exact sequence of CRC output:
Previous CRC Value | Input | Next CRC Value | Next FCS Value FFFFFF | 00 | 4E08BFB4 | D202EF8D
4E08BFB4 | 00 | 00B7647D | 41D912FF 00B7647D | 12 | A5EAE0CF | 0CF8A85A A5EAE0CF | 33 | 648CF998 | E660CED9 648CF998 | FF | 82AF68FF | 00E90ABE 82AF68FF | FF | 7E116434 | D3D97781 7E116434 | D3 | BB9FD215 | 57B40622 BB9FD215 | D9 | 07F1A3E0 | F83A701F 07F1A3E0 | 77 | 16C33676 | 91933c97 16C33676 | 81 | F86C1D9B | 2647C9E0The VHDL code I used is below: process(clk) begin if(clk'event and clk = '1') then crc_32_out