SystemVerilog Sequence Coverage Problem?

Hi all,

I am reading some FIFO code by SystemVerilog. But there is a part of code confused me. It seems to count push and pop pair appear times.

But if I have "push1 -> push2 -> pop1 -> pop2", coverage result will give out 4 times or only 2 times theoretically? And why count this number?

//--- Code start property p_push_pop_sequencing; @ (posedge clk) fifo_if.push |=> ##[0:$] fifo_if.pop; endproperty : p_push_pop_sequencing

// coverage of sequences cp_push_pop_sequencing : cover property (p_push_pop_sequencing); //--- Code end

Any suggestions are welcome! Best regards, Shenli

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