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Visual IP Designer is an EDA tool for design entry and integration which enable designers to intuitively build, maintain and reuse their designs using a full graphical approach. Visual IP Designer provides an advanced and fast methodology to develop HDL-based designs targeting ASIC and FPGA. The Visual IP format is able to describe designs at RTL level in a more flexible and attractive way. The automatic code generation feature allows obtaining a high quality VHDL code optimized for synthesis with a non scarified readability.