Latest threads in Field-Programmable Gate Arrays

FPGA clock gating ? Or how to avoid it in this case ?

Hi, So, my problem : I have a netlist of a module. I can't change it, it comes from a big manufacturer and they have no...

3 19yrs

SomeOne

3 19yrs SomeOne

book recommendation for self study in digital logic design

Hi, I am looking for a self study book above the basic introductory level of digital logic design. Looking into what te...

3 19yrs

GHEDWHCVEAIS

3 19yrs GHEDWHCVEAIS

How to make a clock delay?

Do I use not gates to make a small clock delay, for example module my_module (osc,a,b,c); input osc; output a,b,c; reg...

3 19yrs

3 19yrs <anesserm>

Platform Cable USB & Windows 2003 Server

Hello, does anyone of you use this configuration (see subject) to run Chipscope Pro and with a Virtex4 development boar...

3 19yrs

helmut.leonhardt

3 19yrs helmut.leonhardt

uClinux on Spartan 3

Hi. I want to install uClinux on a Spartan 3 XC3S1000. Now I need auto-config.in file to compile uClinux distro! But......

7 19yrs

peppeunz

7 19yrs peppeunz

ethernet MAC and switch

Hello friends, I Have just started going through ethernet.my doubt is what is the main functionality of Ethernet MAC???...

2 19yrs

ashu_19_1980

2 19yrs ashu_19_1980

Xilinx Constraints Editor doesn't work anymore?

Hi: I used to use the Xilinx Constraints Editor (XCE) (right click on the .ucf file under my source file, and open it)...

0 19yrs

crobc

0 19yrs crobc

ANNC: Serial RapidIO Webcast

Lattice is holding a webcast tomorrow Wednesday, January 24, "Serial RapidIO Solutions from Lattice and Mercury Compute...

0 19yrs

bart.borosky

0 19yrs bart.borosky

NIOS II Application startup issues

Hello, I am having a very strange problem with NIOS II not running a specific application. We are using DDR memory runn...

2 19yrs

robd

2 19yrs robd

Good hardware design code re-use strategies, reference book

I am the main hardware designer for the company I work for. I inherited a lot of old, badly written, poorly documented...

5 19yrs

wallge

5 19yrs wallge

FPGA damage from bad bitstream

Does anyone know if it is possible to permanently harm a Xilinx FPGA internally through a bad (accidental or malicious)...

16 19yrs

stephen.craven

16 19yrs stephen.craven

Xilinx plb ipif read fifo

Hi Using xilinx EDK we have implemented a PowerPC program reading data from a vhdl module that is connected through a P...

0 19yrs

rune_dahl_no_spam_thanks

0 19yrs rune_dahl_no_spam_thanks

FPGA power supply design

Hi all, I'm newbie in FPGA, and want to build my own FPGA board. Actually, I already have my own development board (whi...

8 19yrs

kunilkuda

8 19yrs kunilkuda

iMPACT dont shows erase write options with fpga

Hi to all i'm a beginner tryin to build some application with a scraped xc2v3000 after generating a bit file with the I...

5 19yrs

bliscachiocciolinatiscali.it

5 19yrs bliscachiocciolinatiscali.it

XdmHelpers:662

Hi, when I use ISE8.2 to do synthesis and P&R for my fpga (Virtex 4) design, I got such message: WARNING:XdmHelpers:662...

0 19yrs

chenyong20000

0 19yrs chenyong20000

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