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NIOS II Application startup issues

Hello,

I am having a very strange problem with NIOS II not running a specific application.

We are using DDR memory running at 100MHz on a Cyclone II FPGA. The memory was setup in SOPC builder. The clock looks good going to memory on the PCB. We have tested memory and we have seen an issue but yet we can see out to 128Megs (on all boards)

The application downloads to DDR and verifies. The application seems to start to run but then stops at the same address (I believe).

We can get the application to run some what reliably on one board but not the other 6 boards we have. One board would run the application some of the time. It seems that it stops working when I add something new to the FPGA design.

We have written a smaller application and it works everytime out of DDR memory.

Our first run of boards never had this problem. We saw something at the beginning when we were bringing up the second boards and application wouldn't run. The way we corrected this was start a new project then bring everything in again. After that we never saw any problems until we started putting more in the FPGA.

I have looked at hardware, how Nios was setup, what is in Nios, the clocks, the PLLs, how Quartus connects to the pins, etc. I am not sure what to look at now. Has anyone had a problem like this before and how was it fixed? Does anyone have any other ideas? We are currently running Quartus 6.1.

Thanks for any help.

Rob

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Rob
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Deal with the issue. Every bit of the RAM has to work. Run full walking ones then zeros tests on all the address and data lines. Put a scope on the memory and check for ringing and noise.

-- Mike Treseler

Reply to
Mike Treseler

Your symptoms seem to indicate a timing problem or signal integrity issue or possibly a supply voltage issue (in that order would be my guess knowing nothing else about your particular design). Verify that the actual PCB delays on the board and the ddr part timings for the actual device match what is in the DDR Controller settings using the MegaWizard and that you can successfully run through the ddr timing verification TCL script that is (or at least was) an output of SOPC Builder when you do the generate. That script is supposed to verify that the ddr timing on the final routed FPGA design is correct. Other things to look for are just the basic things like....

- signal quality (are the nets properly termiated?)

- Supply voltages (any dips?)

If you haven't done so lately, peruse the ddr controller handbook again for something that you may have overlooked in the design process.

As Mike suggested in his post, getting a simple memory test to walk 0 and 1 across the entire memory is an important test that absolutely must run without fail before even bothering to use the memory for any application.

Kevin Jennings

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KJ

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