Xilinx plb ipif read fifo


Using xilinx EDK we have implemented a PowerPC program reading data from a vhdl module that is connected through a PLB IPIF FIFO.

Reading a single data element of 64bit from the FIFO takes 60 clockcycles. Reading 8 times in a row takes 672 clockcycles. All clockcycles are measured using Xtime and taking overhead into account.

We find the number of clockcycles very high, expecting it to take only a couple of clockcycles to read an element from the fifo.

Are we overestimating the speed of the plb ipif?

best regards Rune

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Rune Dahl Jorgensen
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