Do I use not gates to make a small clock delay, for example
module my_module (osc,a,b,c); input osc; output a,b,c; reg a, b, c; always @ (osc) begin a = osc; b = a; c = b; end
Will this give me delayed clocks?
How to make a clock delay?
Jan 24, 2007
3 Replies
Only if you disable logic optomizations in your synthesis tool....which in most cases is generally 'not' what you want to do. PLL (Altera), DCM (Xilinx) or re-examining the design as to why you think you need a delayed clock is a better approach.
Kevin Jennings
Is there a way to fool the optimizer?
Sometimes you can put a "keep" attribute on the intermediate signals. But this has to be a very bad way of doing things: your design will probably not work on a different device, may be sensitive to temperature, supply voltage, moon's phase, etc.
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