Field-Programmable Gate Arrays

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Minimal design for xilinx?

I want to send off a pcb board design for a xiling xc9536 so that I can experiment with some simple verilog programs. I...
17 comments posted 19yrs
posted by <canest>
17 comments posted 19yrs posted by <canest>

Higher studies

Hi all experts, Does any body tell me about the well known institues for fpga/asic study in Europe where I can start my...
3 comments posted 19yrs
posted by mirzamihsan
3 comments posted 19yrs posted by mirzamihsan

Anyone have a Lancelot card for sale?

Sorry for the spam, but I wonder if there is anyone who has a fpga.nl Lancelot card they would consider parting with. S...
0 comments posted 19yrs
posted by hpa
0 comments posted 19yrs posted by hpa

Webpack-9.1 working on debian / grml

I downloaded Xilix webpack9.1 yesterday, now tonight had some chance to play with it. All works OK on my grml Linux sys...
0 comments posted 19yrs
posted by pNaonStpealmtje
0 comments posted 19yrs posted by pNaonStpealmtje

Forcing a LUT to not be optimized

Hi, I'm trying to create a design that uses a LUT to control routing on a Virtex-II Pro. It's pretty easy to create the...
7 comments posted 19yrs
posted by dpmontminy
7 comments posted 19yrs posted by dpmontminy

Timing analyzer with Virtex 4

Hi, I am designing with Virtex 4, which needs DCM output clk0/90/180/270 at more than 300MHz. I use a ibufg to connects...
8 comments posted 19yrs
posted by chenyong20000
8 comments posted 19yrs posted by chenyong20000

Inferring Xilinx RAM's with Byte enable options

Hello all, does any one have an idea about the related question? what is the type of code written to infer the option me...
1 comments posted 19yrs
posted by anil.janumpally
1 comments posted 19yrs posted by anil.janumpally

how do you code this?

There is a 20 bit counter,with two inputs ,on the rising edge of one input the counter must increment and on the rising...
9 comments posted 19yrs
posted by aramosfet
9 comments posted 19yrs posted by aramosfet

unsigned and signed data in Verilog?

Hi all, I am reading "Coding Guidelines for Datapath Synthesis" from Synopsys. And confused with the example below, why...
0 comments posted 19yrs
posted by zhushenli
0 comments posted 19yrs posted by zhushenli

Datapath design problem?

Hi all, I am reading "Coding Guidelines for Datapath Synthesis" from Synopsys. It says "The most important technique to...
2 comments posted 19yrs
posted by zhushenli
2 comments posted 19yrs posted by zhushenli

Timing Diagram Tool

Does anyone know a decent - FREE - timing diagram cad tool? Thanks
4 comments posted 19yrs
posted by any2willdo
4 comments posted 19yrs posted by any2willdo

ModelSim Leaf Instances

Hello group, I ran into an ugly ModelSim6 warning saying that I had too many "leaf instances" or lines of code, and tha...
2 comments posted 19yrs
posted by bradsmallridge
2 comments posted 19yrs posted by bradsmallridge

Can't assign pins in Webpack 8.2i schematic design

Hi: After further attempts to use Xilinx Webpack 8.2i for Coolrunner XPLA3 I have discovered the following situation wh...
1 comments posted 19yrs
posted by crcarleRemoveThis
1 comments posted 19yrs posted by crcarleRemoveThis

Porting MontaVista Linux on ML403

Hi, I have been trying to port MontaVista Linux 3.1 to ML403 board. The source compilation was successful. I have set u...
4 comments posted 19yrs
posted by sh3.m4y4
4 comments posted 19yrs posted by sh3.m4y4