unsigned and signed data in Verilog?

Hi all,

I am reading "Coding Guidelines for Datapath Synthesis" from Synopsys. And confused with the example below, why split unsigned and signed + and *?

//=====Unintended behavior====== input signed [3:0] a; input signed [7:0] b; output [11:0] z;

// product width is 8 bits (not 12!) assign z = $unsigned(a * b); // -> 4x8=8 bit multiply //============================

//======Intended behavior====== input signed [3:0] a; input signed [7:0] b; output [11:0] z; wire signed [11:0] z_sgn;

// product width is 12 bits assign z_sgn = a * b; assign z = $unsigned(z_sgn); // -> 4x8=12 bit multiply //============================

Best regards, Davy