how do you code this?

Are the two clocks synchronised? (I assume not, since you're building a FIFO). If not, such a circuit cannot be built. Consider what might happen when the two clock edges occur almost simultaneously: the circuit will certainly fail for some (small) delay between the clocks. The usual way to build a FIFO is to use a separate counter for each port. You can compare them to determine fullness. (Hint: use Gray-code counters, not straight binary).

If the clocks are synchronised, it may be possible to re-work the circuit, so the counter sees a single clock, and an UP/HOLD/DOWN control input. That is feasible.

You don't. But consider coding two separate counters and computing the difference between them.

Since you have two separate clock domains, it can get complicated.

If you only need the output (difference) in one of the clock domains, consider re-latching the second domain's counter output on the first clock, to keep the output computation synchronous.

- Brian

you're building a

Well the FIFO is not exactly asynchronous. Since i'm using a single port SRAM that sits outside the FPGA, it cannot handle a simultaneous read and write.I'm designing the state machine such that only one of the signals is asserted to the 20 bit counter at once.If i redesign the circuit to use a single clock with UP/HOLD/DOWN control ,i need to waste another clock cycle.i'm already using 2 clocks for read and 2 clocks for a write operation to satisfy the timing requirements of the SRAM chip.The reason why chose to implement a counter instead of comparing the RD,WR addresses is that, i can generate full, empty signals and also know to size of the buffer at any instant.

you're building a

Can you specify exactly what is meant by "not exactly asynchronous"? The whole thing may turn on that point: if there's a predictable relationship between those clocks, it can likely be exploited. But nobody is building FPGA elements with multiple clock inputs: everything ultimately reduces to simple D-flipflops.

you're building a

exactly what is meant by "not exactly asynchronous"? The

The FIFO will be written by a UART which will get MP3 data from the PC.The uart will use its own clock so that it is easy to generate the standard baud rates.No matter whether the inputs to FIFO is synchronous or asynchronous, the state machine is designed to synchronize the wr and rd inputs and carry out a rd or wr operation.Hence the inputs to the 20 bit counter will never be asserted at once, They will be atleast (worstcase) 4 FIFO clocks apart.Thank you

you're building a

exactly what is meant by "not exactly asynchronous"? The

So the write side of the FIFO cannot be running much faster than 115/8 kHz. How fast is the read-side clock? If it's dramatically faster, then just sample the UART outputs into the output clock domain, & do everything there. (ie re-synchronise the UART's ready line, & use the re-sampled edge to trigger a read of its data lines. Since RD & WR to most UARTs are asynchronous to the shift clock, the UART has done your work for you.

SRAM = synchronous random access memory, the memory must have its own clock

So, it's much easier if you have another 3rd clock running the FIFO, this clock must be faster than the two inputs, then you need to generate the the FIFO's WE and RE pulses base on the rising edges of the two inputs

Now consider the counter, it's also running by the SRAM clock, the counter will count up with WE and count down by RE

Dunno if you can do this without the 3rd clock

computing the

computing the

The RAM used here is Static RAM(ISSI IS61LV25616AL Static RAM) not Synchronous RAM, sorry if i misled you.The 20 bit counter is to generate buffer full and empty signals and also to monitor the size of the buffer used at any instant.The rd and wr addresses are generated separately.I'm planning to use LFSR's to generate the RD and WR addresses.

Ahh, I missed it not you, I haven't touch that static ram for long time :)

But my theory is the about same. Even though the FIFO has no clock, the data/address and read/write enables would be synchronized when they going in and out your fpga