Field-Programmable Gate Arrays

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Xilinx USB download cable

Hello everybody, today I tried to use an USB Xlinix Multilinx cable (DLC6) with ISE 9.1. To OS is Windows XP, SP2. When...
5 comments posted 19yrs
posted by fras
5 comments posted 19yrs posted by fras

xilinx 8.2 xps debug problems

Hi I am working with an xilinx xup board. 8.2 sp1 ise + 8.2 edk. I am starting creating a design with ppc running from...
2 comments posted 19yrs
posted by llenz
2 comments posted 19yrs posted by llenz

Simulation of DCM with Xilinx 8.2 and Modelsim 6.1

Hello, for some reason I still don't understand, when I simulate my Post Place & Route model, the DCM that was configur...
0 comments posted 19yrs
posted by maybetooparanoid
0 comments posted 19yrs posted by maybetooparanoid

EDK-Modelsim XE

Hello, I am using the Xilinx EDK to perform simulations of the embedded PowerPC on a Virtex 4 Fx. I have had no success...
1 comments posted 19yrs
posted by olive_dominguez
1 comments posted 19yrs posted by olive_dominguez

Any UK mirror for ISE 8.2i SP2?

The Xilinx server is taking forever to serve the latest service pack. Does anyone know of a UK mirror for it or can anyo...
2 comments posted 19yrs
posted by shareef.jalloq
2 comments posted 19yrs posted by shareef.jalloq

IP Protection

Hi all, I want to know whether xilinx provides any features to encrypt the netlist files(.ngc or .ngd) before deliverin...
1 comments posted 19yrs
posted by nagarajputti
1 comments posted 19yrs posted by nagarajputti

On-chip randomness (V4FX)

Hi, I'm working on a V4FX design that contains cryptographic primitives. To secure the system against an expected threa...
15 comments posted 19yrs
posted by jetmarc
15 comments posted 19yrs posted by jetmarc

CONDITION VARIABLES IN XILKERNEL

Does Xilinx microkernel (xilkernel) support for Condition Variables in Pthread?. That is, can I use code such as: pthrea...
0 comments posted 19yrs
posted by pbantunez
0 comments posted 19yrs posted by pbantunez

General Number Field Sieve in FPGA

Hi! I've been trying to find some resources on the subject, but can't seem to find much. Has this been done? And to wha...
1 comments posted 19yrs
posted by tlan
1 comments posted 19yrs posted by tlan

Aligning data with clock

I am using a virtex 4. I have an clock input, and another input for bitstream. What is the best way to align the rising...
5 comments posted 19yrs
posted by seabass950
5 comments posted 19yrs posted by seabass950

ML403 board - VGA schematics - wrong pins

Hi, I am trying to do my own vga driver for ML403 board. I have done the same vga driver for other boards, so I only ha...
7 comments posted 19yrs
posted by gsosar
7 comments posted 19yrs posted by gsosar