Field-Programmable Gate Arrays

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Where is help for schematic entry?

I can't find any help files about schematic entry, please advise?
2 comments posted 19yrs
posted by <carshie>
2 comments posted 19yrs posted by <carshie>

Synthesis of DSP algorithms

Hello, Since any datapath design is essentially a control statemachine, I was wondering about the following: Say I have...
0 comments posted 19yrs
posted by mloulah
0 comments posted 19yrs posted by mloulah

DDR FPGA Design

I'm planning an FPGA design that will be using SDRAM (DDR Winbond W9425G6DH5) and NAND Flash (ST NAND018W3B2AN6E). I'm...
14 comments posted 19yrs
posted by blinkingCursor
14 comments posted 19yrs posted by blinkingCursor

cpld version?

I want to order a xilinx xc9536 cpld. In one catalog I found the following 9536 XLX 44 PLCC In-system Programmable FLAS...
17 comments posted 19yrs
posted by <carshie>
17 comments posted 19yrs posted by <carshie>

Graphics demo using FPGA?

Hi. Just interesting, does anybody used FPGA to produce real-time graphics effects, in the spirit of demoscene? http://e...
9 comments posted 19yrs
posted by Dennis.Yurichev
9 comments posted 19yrs posted by Dennis.Yurichev

UNKNOWN Processor Version (0) in XMD

Hi All, I am a Newbie and I am trying to load my C program on an FPGA using through EDK 8.1i without using BSB (since i...
3 comments posted 19yrs
posted by shantchandrakar
3 comments posted 19yrs posted by shantchandrakar

ahdl --> vhdl

hi, i have project in ahdl (max plus II). Is it possible to convert it to vhdl? I tried to use XPort, but there were err...
1 comments posted 19yrs
posted by spawnek
1 comments posted 19yrs posted by spawnek

Help with Xilinx i/o constracint for ps/2 port

I am designing a PS2 interface for a board with Xilinx Spartan-3 device. The clock and data signals of the PS2 port are...
1 comments posted 19yrs
posted by fpga002006
1 comments posted 19yrs posted by fpga002006

How to use the test bench wave form simulator?

Hello, can anyone explain to me how to use the test bench waveform simulator. I am receiving a clock and another signal...
4 comments posted 19yrs
posted by <boled>
4 comments posted 19yrs posted by <boled>

help with Design Compiler -> Quartus

I have a source code which is compiled by the Design Compiler from Synopsys. I also mapped my technology library to tha...
5 comments posted 19yrs
posted by schseb
5 comments posted 19yrs posted by schseb

XUP Virtex-II Pro

Hello all, Does anybody have a simple example I can load on this board, which works in EDK 8.2 and uses the xsga port?...
0 comments posted 19yrs
posted by wouter.vanhauwaert
0 comments posted 19yrs posted by wouter.vanhauwaert

Differential pairs per Bank

Hello, we want to use a Spartan-3A to collect signals of about 100 differential lines. This type offers the possibility...
7 comments posted 19yrs
posted by tom.reinemann
7 comments posted 19yrs posted by tom.reinemann

linuxppc on ML403

Hi Dear All, I have one ML403 board with ppc405 core,and I want to port LinuxPPC on it. are there anybody tell me, wher...
0 comments posted 19yrs
posted by szricky
0 comments posted 19yrs posted by szricky