hi,
how does z-transforms (basically the mathematical techniques in designing digital systems) map with FPGA implementations. is there a systamatic flow that is used in the industry when implementing a given algorythm in verilog/VHDL.
thank you
how does z-transforms (basically the mathematical techniques in designing digital systems) map with FPGA implementations
Jan 30, 2007
2 Replies
CMOS, This is a very broad topic. I'd suggest you read the following article from a recent Xilinx magazine.
Regards,
Derek
You might ask on comp.dsp, for the more mathematical side.
Otherwise, the easy answer is that Z**(-1) is a register (set of FFs). I like systolic arrays, though they may or may not work for your application.
-- glen
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