Initialisation of two dimensional array to known non-zero values in verilog

Jan 30, 2007 2 Replies

To declare and initialise a one-bit register in verilog we use the following statement reg one_bit_reg=1'b0;



Similarly, to declare and initialise a one dimension reg (e.g. 8-bit) we can write reg [7:0] reg_len_8=8'd0;



We can declare a two dimensional array (e.g. 16x8-bit) as reg [7:0] reg_dim_2 [15:0];



But how can we initialise this array in the same statement? or How do we declare the initial state (known non-zero values) of an array without using extra logic (especially when implementing on hardware (FPGAs))?



For simulation purposes, you may use an init loop:

initeger i; init for (i=0;i

Adtually, the statement:

initial $readmemh(reg_dim2,"init_file.txt");

Should wordk for synthesis and simulation. At least, xst claims to support it, and all simulators support it.

Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."

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