Field-Programmable Gate Arrays

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Linux on Virtex 4?

Does anyone have experience or know the best solution to get Linux on Virtex 4? I heard something about MicroBlaze as a...
1 comments posted 19yrs
posted by -
1 comments posted 19yrs posted by -

Change ROM contents, .bit file

Hi, I would like to edit ROM contents in Virtex-4 .bit file (in order to avoid re-synthesis/P&R). Is there any informat...
2 comments posted 19yrs
posted by mountaineering
2 comments posted 19yrs posted by mountaineering

Xilinx Timing Constraints and failures

Hi, I am using Xilinx ISE 8.2 (SP3) targeted at a spartan 3 device. We are attempting to use an FPGA for F/W and proof...
1 comments posted 19yrs
posted by moogyd
1 comments posted 19yrs posted by moogyd

USB 2.0 Streaming using FPGAs

Hi All, I was wondering if its possible to stream data at 480Mbps from a PC to a USB 2.0 port on a FPGA development boa...
18 comments posted 19yrs
posted by bkamakot
18 comments posted 19yrs posted by bkamakot

Global Clocks in Xilinx ISE

Hi, I'm programming on a Spartan-II in ISE. I have a few questions about the clk signals and .ucf files. I have assigne...
6 comments posted 19yrs
posted by ian.peikon
6 comments posted 19yrs posted by ian.peikon

question about DCM usage in virtex 5

When I use DCM in virtex 5 and do the simulation, the modelsim 6.2e gives the following error message: Failure: (vsim-3...
3 comments posted 19yrs
posted by hy34
3 comments posted 19yrs posted by hy34

Conversion from Xilinx ISE 7 to 8 fails

Hi, I tried to open a project that I created with ISE 7.1, with ISE 8.2 (both with latest SP). I get the following erro...
0 comments posted 19yrs
posted by kronkarp
0 comments posted 19yrs posted by kronkarp

bram can't store elf

Hi, I'm new to using the EDK and need some help. I'm working on a microblaze system which has become to big for the BRA...
3 comments posted 19yrs
posted by daniel.blake2
3 comments posted 19yrs posted by daniel.blake2

virtex-II DCM phase shift problems

Hi all, Right now I'm developing a board using virtex-II FPGA, and want to implement a function using the DCM to offer...
3 comments posted 19yrs
posted by jacklee1985
3 comments posted 19yrs posted by jacklee1985

Problem with verilog program

I receive the following error ERROR:Xst:899 - "a1.v", line 8: The logic for does not match a known FF or Latch template...
6 comments posted 19yrs
posted by <canest>
6 comments posted 19yrs posted by <canest>

Problem with pin assign using CASE

I need urgent help. Perhaps it is just a simple problem, but I don't know how to solve it. I try to design a simple CPL...
3 comments posted 19yrs
posted by hans-georg.stoehr
3 comments posted 19yrs posted by hans-georg.stoehr

Minimal design for xilinx?

I want to send off a pcb board design for a xiling xc9536 so that I can experiment with some simple verilog programs. I...
17 comments posted 19yrs
posted by <canest>
17 comments posted 19yrs posted by <canest>