Hi,
I am using Modelsim to simulate placed-and-routed Xilinx design. I have noticed that in some cases iopath from sdf is being treated as a transport delay and in some other as inertial delay, although the type of the cell is the same (for example, x_buf_pp). Could someone tell me why is this happening and is there a way to change it?
Thanks in advance!
Ruzica
Hi,
I am using Modelsim to simulate placed-and-routed Xilinx design described in VHDL. I have noticed that in some cases iopath from sdf is being treated as a transport delay and in some other as inertial delay, although the type of the cell is the same (for example, x_buf_pp). Could someone tell me why is this happening and is there a way to change it?
Thanks in advance!
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