I looked at Xilinx' sysnthesis template for double-registering asynchronous signals to avoid metastability problems. They explicitly state that an SRL primitive should NOT be extracted. Why is this?
I have used basically the same Verilog construct in my designs (having not looked at Xilinx' template first) and am fairly certain that SRL primitives ARE used. Is there a problem with this? Is it not advidsable to use SRL primitives as synchronization flops?