Xilinx SRL's and sync flip flops

I looked at Xilinx' sysnthesis template for double-registering asynchronous signals to avoid metastability problems. They explicitly state that an SRL primitive should NOT be extracted. Why is this?

I have used basically the same Verilog construct in my designs (having not looked at Xilinx' template first) and am fairly certain that SRL primitives ARE used. Is there a problem with this? Is it not advidsable to use SRL primitives as synchronization flops?

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The SRL16 is not a master/slave flip flop, so as such, it is not well suited to be used as a synchronizer between an asynchronous domain and a synchronous one.

Basically, for synchronization, you want a master slave FF, and you want it to be incredibly fast.

In V5, the SRL32 (or SRL16 is a master slave design, and this restriction should be removed (IMO).


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Austin Lesea

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