problem while using if or case statements

hai ,

i am vishnu, i am doing my project in verilog using state machine, while using if or case statements i am getting some error . i have coded like this

s4 : begin if ( {gsr,gsy,gsb} == 000 ) begin count

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You didn't show us how you declared gsr, gsy and gsb. I'm assuming that they are single bit. You aren't telling Verilog the radix of your constants. The correct syntax would be:

if ( {gsr,gsy,gsb} == 3'b000 )


I'm not sure if this is even syntactically correct, and if it is, whether it evaluates in the way you think:

else if ( {gsr,gsy,gsb} == 3'b001 | 3'b010 | 3'b011 | 3'b100 | 3b'101| 3'b110 )

You probably mean

else if ( ({gsr,gsy,gsb} == 3'b001) || ({gsr,gsy,gsb} == 3'b010) || ({gsr,gsy,gsb} == 3'b011) || ({gsr,gsy,gsb} == 3'b100) || ({gsr,gsy,gsb} == 3'b101) || ({gsr,gsy,gsb} == 3'b110))

Finally, in your case statement, please assign the same set of signals in every case. In case 3'b000, you assign count and nextstate; in case

3'b001, you assign phaseerror and count. What happens with nextstate? Verilog will synthesize the logic such that nextstate
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Joseph Samson

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