Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF

Here are a few more details about the project of getting this core up and running:

Using the GMII Interface, in trimode I am trying to keep this project inside of ISE , and not use EDK for anything at the moment. The only changed I made to the UCF so far would be the LOC assignments of the RX/TX Signals and with the IDELAYCTRL location. I am still looking more into the IDELAYCTRL location that I should be using since this part is still pretty new to me and I haven't done much work with constraints past basic pin assignment.

As well, if anyone know any good sites that go over the constraints used in these UCF files, please let me know. I do already know about Xilinx's scattered PDF files on their site which for me at least do not always tend to be that clear, so anything other than those (such as some .edu site with lab handouts, etc) would be great!

Thanks again,

-Mark

Mark,

Which core exactly are you talking about? I have successfully used ll_temac EDK core, although I had to tweak it somewhat to implement RGMII interface. This might be already done in the latest revision though. Also, my design was based on the GSRD reference design.

/Mikhail

I have used the Coregen TEMAC core in several designs. The generated files include the LOC for IDELAYCTRL in the source code, so I would recommend you remove that first. .e.g. my vhdl wrapper temac_v3_2_block.vhd has the line below. You can either comment it out or remove it completely. attribute loc of dlyctrl : label is "IDELAYCTRL_X2Y1";

If you don't care about the IDELAYCTRL replication, you don't even LOC it in UCF. If you really want to know which pins are associated with which IDELAYCTRL, you can use ADEPT to view that

The other thing you may need to play with is the delay on gmii_rx_clk. You can change it (IOBDELAY_VALUE of IDELAY block) either in source code (rx_clk_gen.v/vhd) or in UCF.

HTH, Jim

Mikhail,

Right now the core I am working with is the Embedded Tri-mode Ethernet MAC Wrapper 4.4 from in the current version of CORE Generator. I am not trying to use EDK at the moment to keep things easier to manage since I am not as familiar with EDK as I am with ISE.

Thanks Jim!

I will go ahead and try to use your advice, as well as to use the 3.2 versions which seemed to work with your design and I will post back on what I can manage to get done. I may not be able to get back for a while since I am currently trying to get some other things finished up, but this needs to be completed soon, so I will have to be working on it shortly. As well, do you know of any sites that may use this core in an example design, such as a .edu site or the like?

-Mark