Hi everybody! I felt in a very strange situation: I'm working with an FPGA BOARD: -2 Virtex-4LX -1 Quick LVDS bus between the 2 FPGAs. -1 INPUT from an external board. -1OUTPUT to the same external board. I use for these quick interfaces ChipSync (Local clocking ressources
+ISERDES+OSERDES). When I make my tests for the internal bus (the connection between the 2 FPGAs) I have no problems: >1Gb/s for each LVDS line. Since the external board is not yet ready to use, I use a small loopback board to connect the output of my board to the input of the same boad (the FPGA board). This board INVERTS LVDS PAIRS ie: if I have an output {XP,XN} I get the input {XN,XP}. ({A,B}=A on P pin and B on N pin). When I make the same tests it doesn't work even on small frequencies. and the use of IDELAY DOESN'T HELP.Please help me Mehdi