Field-Programmable Gate Arrays

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Manual LUT - AND function mapping problem

Dear all I am trying to manually map "2-bit AND" function into single slice, with no luck -: I type the commands below...
2 comments posted 19yrs
posted by pasacco
2 comments posted 19yrs posted by pasacco

gated clock

hi, I have a design with two clock that I want to mux toward a single clock like this with mode select CLK
6 comments posted 19yrs
posted by patrick.melet
6 comments posted 19yrs posted by patrick.melet

LZW compression and decompression in vhdl

Hi, can somebody help me to find an implementation of LZW compression/decompression algorithm in VHDL? Thanks a lot. Eri...
1 comments posted 19yrs
posted by erixx
1 comments posted 19yrs posted by erixx

CPLD erase??

Working with a coolrunner2 CPLD. Is there a way to erase whatever has been programmed into the CPLD, without using JTAG?
3 comments posted 19yrs
posted by mtsukanov
3 comments posted 19yrs posted by mtsukanov

Data width in Block ram

I have to generate a block ram in xilinx. The data width is not fixed and it will be changed according to the requireme...
5 comments posted 19yrs
posted by threeinchnail
5 comments posted 19yrs posted by threeinchnail

Austin the Altera Mole

Is he? First Austin admits Cyclone 3 is lower power than S3E or V5. Then he tells us to stop using XST for real designs...
15 comments posted 19yrs
posted by rickystickyrick
15 comments posted 19yrs posted by rickystickyrick

Why is Xilinx's WebPACK so inferior?

I've been using the Xilinx Webpack 8.2i since sometime in November, and I've become so irritated with their software th...
50 comments posted 19yrs
posted by thutt151
50 comments posted 19yrs posted by thutt151

Virtex-II block RAM problem

Hello, I am running into a strange problem with the dual-port block RAM in Virtex-II and at this point have run out of...
15 comments posted 19yrs
posted by dimtey
15 comments posted 19yrs posted by dimtey

Zero-Valued Data Out of Chipscope ILA?

Hello, I have a design on a SX55 that contains of two complex (real +imaginary) datapaths. I've been trying to debug th...
2 comments posted 19yrs
posted by killerhertz
2 comments posted 19yrs posted by killerhertz

1.8V config proms for Cyclone 2s

Hi folks, Is it possible to get EPROMs for Altera (Cyclone 2) devices that work at 1.8V? I appreciate the help and insig...
0 comments posted 19yrs
posted by fpgabuilder-groups
0 comments posted 19yrs posted by fpgabuilder-groups

FF's are inffered instead of distributed RAM

i have a byte array of size 10 and i need to shift values in the array to left by 5 positions in 5 clocks. here is the...
2 comments posted 19yrs
posted by manusha
2 comments posted 19yrs posted by manusha