I would really appreciate if you could give me some insight on the following
-Can you guide me to a link/example which runs thru the process of dynamic reconfiguration on Virtex2/4 step by step.I read and understood the paper you guys pointed to.
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I have also read the documentation on the Xilinx website(userguide etc).I would like to see an example implementation(could be trivial example).Else if you guys could give me some suggestions on a trivial example for me to test and see that partial dynamic reconfig actually works using the ICAP.
-Also,from the paper I would assume that the patial bitstreams would be generated using the FPGA editor from Xilinx.Now assuming I want to have a set of bit streams loaded on to the Internal memory buffer of the microblaze,How do I do that i.e how do I store the bit streams on the microblaze(internal memory).I am using an ML310 board.
If you're wondering whether it actually works, yes it does, and very nicely.
The bitstreams would in fact be generated by bitgen, though you could use HDL source or EDIF netlists or FPGA Editor to generate the .ncd that bitgen would use. You can pass "-r " to bitgen to ask it to generate a bitstream that only includes frames that differ between your original bitstream and your new bitstream. That's how partial bitstreams are created.
Because you're interested in active reconfiguration (i.e. reconfiguration of the FPGA while it's running), you also have to tell bitgen not to shut down the device, by passing "-g ActiveReconfig:Yes" to bitgen. Otherwise the very first thing the bitstream will do is stop the FPGA, and since you're reconfiguring the device from the inside, you'll have aborted the reconfiguration, with nothing to re-awaken the device.
There are a few other considerations, such as not corrupting frames that contain LUT RAMs (including SRL16s) or BRAMs, but you probably don't need to worry about that quite yet.
I'm not sure exactly what you're asking. When you speak of the "internal memory buffer of the microblaze", are you thinking of BRAM inside the FPGA, as opposed to external memory on the ML310 board? (And do keep in mind that the XC2VP30 on your ML310 only has about 306 KB of BRAM.)
What exactly are you running? Is this uClinux on a MicroBlaze on the ML310? (I'm using regular Linux on PowerPC on the XUP V2Pro, so I can't directly provide you with an example.)
And what are you trying to do with this? Or are you simply trying to verify to your own satisfaction that the concept does work?
As for talking to the ICAP, you can use John's ICAP driver if you're running uClinux. Or you can use
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if you're running regular Linux (at least for kernel 2.4.x). Or you can always talk directly to the Xilinx xhwicap driver, instead of going through a Linux/uClinux driver. Documentation for the xhwicap driver is available with the EDK, and the source for John's driver or for my driver may help you better understand how to talk to the xhwicap driver.
If you start making progress with this, then consider the following correction to the xhwicap driver:
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This correction will spare you some grief if you're trying to write multiple frames without aligning them on boundaries. Probably something that you don't need to worry about yet though.
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