I'm designing filter system called IIR filter on the FPGA kit, but it doesn't work when I implement on FPGA. When i iput the signals, the output results seem to not get any thing. I do not know whether my source code is wrong or another reason. The FPGA kit operate normally with other sources which i loaded in the past.
Can anyone give me some advices to test what parts in my project do not work or give me some idea to test anything. I am in the mess. I hope everyone can show me.
Hi everyone! Thank you for your reply! I used ModelSim to simulate. The result is the same when I canculate by calculator. But when I implement on FPGA, it don't work too. I design IIR filter with 10 orders. I use Matlab to generate coefficients for filter (b(k) and a(k)). For coefficient "b", I multiply with 2^14 and multiply with 2^5 for coefficent "a". After that I round them. These coefficients stored in LUT. I use SDA for filter. Because I think IIR filter include tow FIR filter. One filter with coefficient "b" and one with coefficient "a". Is it right?
Check your synthesis log to make sure your design did not get 'optimized' away. If you forgot some control signals somewhere, it is possible that synthesis deduced that some of your design had static elements, removed them to optimize, then deduced that everything else is now unconnected and removed that as well.
BTW, also make sure your VHDL agrees with your board's reset polarity.
A 10th order filter is very prone to overflows because some sections will have a high Q factor. You said you simulated the design; try to do that again with a maximum amplitude input signal and see what happens.
It is probably better to create several 4th order filters and cascade these. However, this may deteriorate the filtering result.
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