Field-Programmable Gate Arrays

how to use and calculate prom checksum in prm file.

this is part of the prm file PROMGEN: Xilinx Prom Generator J.30 Calculating PROM checksum with fill value ff Format Mc...

0 comments posted 19yrs

posted by ustcmayichao

0 comments posted 19yrs posted by ustcmayichao

broken mb-gcc -O2 ?

Hi, I'm compiling this code for microblaze gcc void uart1_printchar(unsigned char c) { while( (*(unsigned char *) UARTS...

2 comments posted 19yrs

posted by manuel-lozano

2 comments posted 19yrs posted by manuel-lozano

DCM_STANDBY macro in Virtex-4

I was obliged to go back to Virtex-4 Stepping Level 1. So I'm now faced with the DCM problems. Should I use the DCM_STA...

4 comments posted 19yrs

posted by taileb.mehdi

4 comments posted 19yrs posted by taileb.mehdi

Question about initializing the ram value in test bench

How do i initialize the ram value in test bench? And how do i read back the value. The following codes is what i have t...

2 comments posted 19yrs

posted by shelai

2 comments posted 19yrs posted by shelai

How much time margin should I give to a SDRAM interface via FPGA?

My altera FPGA is connected to a SDRAM on the prototype board. Assume the clock frequency is 100MHz, how much margin sho...

3 comments posted 19yrs

posted by newsreader

3 comments posted 19yrs posted by newsreader

Spartan-3A XC3S1400A development board?

Greetings, Would anyone happen to know where if could purchase an FPGA development board with the Xilinx Spartan-3A XC3...

5 comments posted 19yrs

posted by News5

5 comments posted 19yrs posted by News5

Altera ASMI_PARALLEL megafunction (EPCS4/CycloneII)

I'm using a EPCS4 to configure my CycloneII in AS mode. >From my design I'm trying to access the contents of the EPCS v...

0 comments posted 19yrs

posted by njelliott

0 comments posted 19yrs posted by njelliott

microblaze bootloader

Hi, I am using XPS to program my application onto the Xilinx Virtex2 pro board. The size of the application is upto 1 M...

0 comments posted 19yrs

posted by yash.r.modi

0 comments posted 19yrs posted by yash.r.modi

ISE on Fedora?

I am running Fedora 6, and I am having trouble installing ISE WebPack. When I run the setup program it tells me that I...

4 comments posted 19yrs

posted by boyscout

4 comments posted 19yrs posted by boyscout

Config PROM for Spartan II

Hi all, at the moment, we are using AT17LV010 configuration devices for a spartan 2S100. I have to look for a different...

5 comments posted 19yrs

posted by markus.knauss

5 comments posted 19yrs posted by markus.knauss

Static RAM implementation with VHDL

Hi Dear all, I need an implementation of a STATIC RAM with VHDL; I need this RAM to work with/without read buffer and wi...

2 comments posted 19yrs

posted by zahra.lak

2 comments posted 19yrs posted by zahra.lak

Help with a face recognition system

Hi all, I am a Computer Science student in my final year. My graduation project is to build a face recognition system (...

18 comments posted 19yrs

posted by islam.ossama

18 comments posted 19yrs posted by islam.ossama

Sysgen compilation target

Hello, I am trying to create a new compilation target for SysGen and I found that the documentation is not complete and...

0 comments posted 19yrs

posted by (use_my_name_here)-34

0 comments posted 19yrs posted by (use_my_name_here)-34

Another simple DCM question

I have a design where I want to have 2 DCMs, each with there own clock source come up with some known phase. The two cl...

3 comments posted 19yrs

posted by lecroy7200

3 comments posted 19yrs posted by lecroy7200

ModelSim VHDL Pragmas

Hi All, In one of my VHDL designs I have a section of code that I want different versions for synthesis than for simula...

9 comments posted 19yrs

posted by ftpeter

9 comments posted 19yrs posted by ftpeter