Field-Programmable Gate Arrays

Transition from ASIC to FPGA

Hi All, I've been working on ASICs for quite a while and now Iam required to move to FPGA domain. I'd be glad if someon...

19 comments posted 19yrs

posted by praneet.dixit

19 comments posted 19yrs posted by praneet.dixit

PCI FPGA Dev Board Suggestions

I'm looking for the perfect FPGA dev board for a project I'm contributing to. I've found one that is *almost* ideal, wi...

8 comments posted 19yrs

posted by kunals.spam.account

8 comments posted 19yrs posted by kunals.spam.account

suitability of systolic architecture on FPGA

Hi, I understand that because of the 2d array CLB structure of FPGA, systolic architecture can be mapped efficiently in...

4 comments posted 19yrs

posted by tlenomade

4 comments posted 19yrs posted by tlenomade

having a state machine in a datapath element a bad design practice?

hi, having a state machine in a datapath element a bad design practice? CMOS

2 comments posted 19yrs

posted by manusha

2 comments posted 19yrs posted by manusha

Gray code in asynchronous FIFO design

Why do we use Gray code in asynchronous FIFO? (I am aware that only ONE bit changes in Gray code at a time, but what is...

18 comments posted 19yrs

posted by writeanand

18 comments posted 19yrs posted by writeanand

Interfacing the DAC0808 to FPGA

Hello, I m building a Function generator using an FPGA!! I m almost done wid the Coding part in VHDL. I'd just like som...

1 comments posted 19yrs

posted by sankpalhrishi

1 comments posted 19yrs posted by sankpalhrishi

Digital Receiver chip suggestion

Hi Folks, I've been active on this forum asking questions on digital receiver. Earlier I was doing most of the work in...

5 comments posted 19yrs

posted by saurster

5 comments posted 19yrs posted by saurster

TFP410 acceptable video input timings (trying to run 1280x1024 at 60Hz with clock slower than 108 MHz)

I am trying to get video through an fpga to a texas instruments TMDS transmitter chip (TFP410). I would like see video...

2 comments posted 19yrs

posted by wallge

2 comments posted 19yrs posted by wallge

fifo occupancy bigger than fifo size?

Note: using EDk 8.2.02 with peripheral generated with the wizard with FIFO enabled and one user interrupt that is set t...

4 comments posted 19yrs

posted by cepope

4 comments posted 19yrs posted by cepope

high number of multipliers / low cost

Hello, I need the highest possible number of multiplication operations per second at low cost. I know that several fact...

18 comments posted 19yrs

posted by ryan_usenet

18 comments posted 19yrs posted by ryan_usenet

Can I boot PowerPC without JTAG?

Is it possible to build an application over PowerPC and download to board without the use of JTAG?. I have a non Xilinx...

1 comments posted 19yrs

posted by pbantunez

1 comments posted 19yrs posted by pbantunez

Problem with PHY clocks on Spartan 3E Starter Kit

Hi, I am designing a ethernet block using the Spartan 3E Starter Kit. The design will be using the RX and TX clock prov...

1 comments posted 19yrs

posted by roger.jons

1 comments posted 19yrs posted by roger.jons

Conceptos about VCCINT,VCCAUX,etc

Hi!, Maybe this doubt is stupid but nobody has explained it to me so could you help me? What are the functionality of t...

1 comments posted 19yrs

posted by jmunir

1 comments posted 19yrs posted by jmunir

MIG under Linux

Hi everybody, Did someone tried to install MIG under Linux using Wine? Cheers Mehdi

0 comments posted 19yrs

posted by taileb.mehdi

0 comments posted 19yrs posted by taileb.mehdi

Looking for Memory Recommendation for Spartan 3E 1200

Hi everyone, I'm working on a Board for Bus Interfacing and some Audio Processing, which will use Spartan 3E 1200 and t...

7 comments posted 19yrs

posted by matthias.einwag

7 comments posted 19yrs posted by matthias.einwag