I am designing a ethernet block using the Spartan 3E Starter Kit. The design will be using the RX and TX clock provided by the SMSC PHY on FPGA pins T7 and V3 on the Spartan 3E Starter Kit. I have problems getting the design to work and when I started to look for errors I found that the RX clock from the PHY doesn't seem to be possible to use as a clock.
I made a simple counter which flashes a led in 2 Hz using first the TX clock from the PHY as the clock input and then the RX clock as the clock input. When I'm using the TX clock everything works fine and when I'm using the RX clock I get no activity at all. I have verified that I have a clock output from the PHY using an oscilloscope.
If I instead run the counter on the 50MHz clock and sample the RX or TX clock and increment the counter when an change on the RX or TX clock signal has occured it works fine using any of the input clocks from the PHY.
One could suspect some problems with the input buffers in the FPGA but since it works using the TX clock I cant see that it is a problem in the FPGA. It is a very confusing problem, can you give me some help what I am doing wrong?