Digital Receiver chip suggestion

I'm surprised it doesn't also have to receive 406MHz to be compatible with the new ELTs and EPRBs.

The FPGA can be made to work, but you'd need a fast ADC to do it without an analog mix to some convenient IF. There are several gigasample ADCs out there, but they are no more than 8-10 bits, which may not give you the dynamic range you need. If done on an FPGA, much of the receiver can be shared by all 4 channels. Really only the NCO, mixer and first stages of your DDC need to be dedicated to single channels, and that's assuming sampling at hundreds of MHz. The lower your sample rate coming in, the easier it is to share hardware among channels. The nice thing with this application is the bandwidth is pretty much just audio, so there is room for lots of decimation. With careful design, you could get a 4 channel receiver that samples at 500 MHz on the input into a smaller V4SX device. If you look at my website gallery at

there is a floorplan of a 10 channel digital receiver that samples at 500 MHz, and includes the phase and amplitude twiddles for beamforming. The device is a Virtex4 SX55, which is being run at a fairly comfortable 250 MHz. The ADC presents two samples in parallel per clock. In this case,the output from each channel is programmable between 5KHz and 40 MHz, which is a much wider range than you'd need. In that image, the logic that is dedicated to each channel is clearly visible as 10 discrete blocks. The logic at the middle bottom is I and Q filters that are shared among all 10 channels on a time multiplexed basis, and the loose stuff up the middle is extra stuff for interfacing and control.

The need is to reduce the analog front end and also the risk in the FPGA. By risk, I mean, with such a high frequency design, comes tighter control on the design. I am trying to get a healthy balance. I agree with you that its going to be hard to digitize the RF directly. I should work on the analog downconversion to IF. The more I think about it, the more redundant the chip gets (AD6654). I think, by carefully considering undersampling techniques on the IF, the FPGA design can be made easier. The kicker is that i'll have to have 4 ADCs to do the job on the FE. I do appreciate your input. I did get Matlab (finally...my manager cringed paying $4500 for the license re-activation) so the modeling should be insightful.

Be careful with undersampling, as it puts stringent jitter requirements on the ADC and it's clock that can be difficult to meet in the real world, especially with carrier frequencies above 100 MHz.

If you do have analog downconversion to an IF, you generally will need separate ADCs unless all your frequencies of interest are within a bandwidth that is narrower than Fs/2. In your case, I think you have two (three if you also do 406 MHz) bands that do not have overlap and are not adjacent. In that case, you ought to be able to use a front end for each band, and then have each channel select which input band to use and then tune from that band digitally. That way you'd need only 2 ADCs (3 if you cover 406 MHz too) rather than the 4 you'd need by having one for each channel.

Also, do you have a requirement to tune frequencies other than the emergency frequencies (121.5, 243 and 406), or do you just need to receive the beacon frequencies? If you just have 121.5 and 243, you may be able to play some tricks with aliasing with your front end mixer to put both at the same IF.

We're hitting some slightly different bands, but the general concept is the same. We're not trying to sample different bands simultaneously though.

IIRC, our HW folks chose the Linear LTC2227. It is nicely low in power draw, is single 3V supply, and it handles undersampling pretty well. For instance, we're driving it with a 25.6 MHz clock rate with a 380 MHz IF (5 MHz BW signal in something like the 11th aliasing band).

The bits go into a TI "Graychip" GC5016 (I figure that's who you're referring to when you said Grayscale). We use a small Altera Cyclone II to package this data for sending to a AD Blackfin DSP (BF537?). The Blackfin can run Linux (uCLinux), which is pretty impressive for a cheap low power chip.

Like one of the other responders said, you could pick your clocking rate and/or mixer frequencies (if any) so that two (or more) of your bands fall into different parts of your (folded) spectral response. The narrower each of your bands are and the higher the clock rate the easier this gets to plan. Then your DDC can pick each channel off regardless of band. Remember that depending on the folding and mixing your frequencies might be "reversed." You usually can tell the DDC to conjugate the output to get the net result straight.

HTH,

Marty

Comprendi!!. I think these are really valuable solutions. I do agree, after some consideration, that with a little bit of modeling upfront, we can reduce the number of ADCs from 4 to 2 and then do the selection in the FPGA through DDS/filters. When you say, "that depending on the folding and mixing your frequencies might be "reversed." You usually can tell the DDC to conjugate the output to get the net result straight", do you mean, genearate negative sine, cosine (if using a Xilinx DDS core) to get the frequencies straight?