TFP410 acceptable video input timings (trying to run 1280x1024 at 60Hz with clock slower than 108 MHz)

I am trying to get video through an fpga to a texas instruments TMDS transmitter chip (TFP410). I would like see video out at 1280x1024 at 60 FPS. The VESA spec calls for this to be clocked at

108 Mhz. But if you look at the actual amount of data (1280x1024x60 = 78.6 MHz) 108 Mhz is alot of overhead for the actual number of valid pixels that need to be pushed through the system.

The FPGA I am using (a stratix I) doesn't want to run this fast. I would like to generate my video at a slower clock speed (with less blanking time). Does anyone know if the TFP410 will accept input video with less blanking time than the VESA spec allows for?

I have been experimenting with slower clock rates but can't seem to get them to work with the blanking intervals / timing parameters i have chosen.

I wondered if there was some formula that I needed to follow.

I have asked TI about this and they have been unhelpful.

Reply to
wallge
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The FPGA will run plenty fast, but you probably need to fix your design if it doesn't meet your timing requirements.

You cannae change the laws of physics. The DVI transmitter might be capable of transmitting with near-zero blanking but the monitor at the other end will have none of it. In order to compress the data stream coming out of your hypothetical slowed-down video source into a pixel stream at a 108MHz dot clock, something somewhere is going to have to buffer a whole lot of video data to effect the rate change. The best candidate for that "something" is really the FPGA you're designing.

Google for VESA GTF (General Timing Formula).

-Ben-

Reply to
Ben Jones

Through some trial and error, I was able to get video out of TFP410 by sending it a pixel clock of 90 MHz with 1280x1024 active pixels and 1407x1066 total pixels. Am I breaking the laws of physics? I'm not using an analog CRT after all. I am using a digital Flat panel.

Reply to
wallge

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