I am trying to get video through an fpga to a texas instruments TMDS transmitter chip (TFP410). I would like see video out at 1280x1024 at 60 FPS. The VESA spec calls for this to be clocked at
108 Mhz. But if you look at the actual amount of data (1280x1024x60 = 78.6 MHz) 108 Mhz is alot of overhead for the actual number of valid pixels that need to be pushed through the system.The FPGA I am using (a stratix I) doesn't want to run this fast. I would like to generate my video at a slower clock speed (with less blanking time). Does anyone know if the TFP410 will accept input video with less blanking time than the VESA spec allows for?
I have been experimenting with slower clock rates but can't seem to get them to work with the blanking intervals / timing parameters i have chosen.
I wondered if there was some formula that I needed to follow.
I have asked TI about this and they have been unhelpful.