Latest threads in Field-Programmable Gate Arrays

How do I constrain Xilinx to implement multi-cycle paths?

Due to RAM access, I calculate data on rising edge while feed into the RAM on negedge edge of clk_100m_i, which is 100M...

1 19yrs

newsreader

1 19yrs newsreader

PLB Master to communicate with the BRAM

Hi, I need to make an IPIF PLB MASTER and I have some question about this purpose, -what is the IP2IP_Addr bus ? -why t...

0 19yrs

lpaulo07

0 19yrs lpaulo07

No login in uClinux (Petalinux)

Is there some method to avoid "login prompt"?. The reason is that I have designed an application over uClinux and I wan...

2 19yrs

pbantunez

2 19yrs pbantunez

Are there Quartus II Web Edition limitations?

Hello! I have a simple question: Are there any limitations to the Quartus II software when I use a web edition liscence...

5 19yrs

maik

5 19yrs maik

Back annotating to RTL

Tracing timing violations in the post-p&r generated netlist can be cumbersome with all signal merging/renaming and inse...

2 19yrs

elshoukry

2 19yrs elshoukry

spartan 3e availability

If spartan 3e are really in mass production, why is it, that this kits: DO-SP3E1600E-DK-UNI-G are never available ? Not...

0 19yrs

emu

0 19yrs emu

SETUP & HOLD time confusion

In the Xilinx Synthesis and Simulation Design Guide there is this phrase: "While Xilinx data sheets report that there a...

11 19yrs

mhs000

11 19yrs mhs000

XPS behavioral simulation fails: the design is not loaded

After designing a peripheral and checking that it is working with the BFM simulation, I am trying to simulate the whole...

4 19yrs

le_marq

4 19yrs le_marq

Problem with EDK 8.2 MicroBlaze Tutorial

I am trying to work through the "EDK 8.2 MicroBlaze Tutorial in Spartin 3" When I get to the point of "Generate Program...

0 19yrs

scot.willis

0 19yrs scot.willis

Changing LUT input size in synthesize

Dear all, I'm doing research on FPGA's LUT input size. And i'm using synplify pro to synthesize vhdl/verilog to edf for...

1 19yrs

yuchiwai

1 19yrs yuchiwai

EDK + XMD

Hi, Here is my problem. My memory map is as follows: ISBRAM : 0xFFFFE000:0xFFFFFFFF SDRAM : = 0xF0000000:0xF1FFFFFF I d...

1 19yrs

eascheiber

1 19yrs eascheiber

how two sine signals are multiplied in VHDL language

hi all, iam doing projevt on Digital down converter.In that i need to multiply RF signal and LO signal . which type of...

2 19yrs

kanthi.siddela

2 19yrs kanthi.siddela

Which are the best books about CORDIC algorithms and applications

Hi, I want to buy two books on CORDIC. One is focused on CORDIC theory and algorithms, another on CORDIC applications....

15 19yrs

wtxwtx

15 19yrs wtxwtx

XST and Verilog $readmemh

In theory, XST claims to support the Verilog $readmemh to initialize memory. I'm using the latest 9.x s/w verion. I loo...

1 19yrs

johnp3+nospam

1 19yrs johnp3+nospam

Timing violations though constraints have been met

I keep on getting Setup time violations from ModelSim despite the fact that my design successfully placed and routed wi...

3 19yrs

mhs000

3 19yrs mhs000

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