Field-Programmable Gate Arrays

No login in uClinux (Petalinux)

Is there some method to avoid "login prompt"?. The reason is that I have designed an application over uClinux and I wan...

2 comments posted 19yrs

posted by pbantunez

2 comments posted 19yrs posted by pbantunez

Are there Quartus II Web Edition limitations?

Hello! I have a simple question: Are there any limitations to the Quartus II software when I use a web edition liscence...

5 comments posted 19yrs

posted by maik

5 comments posted 19yrs posted by maik

Back annotating to RTL

Tracing timing violations in the post-p&r generated netlist can be cumbersome with all signal merging/renaming and inse...

2 comments posted 19yrs

posted by elshoukry

2 comments posted 19yrs posted by elshoukry

spartan 3e availability

If spartan 3e are really in mass production, why is it, that this kits: DO-SP3E1600E-DK-UNI-G are never available ? Not...

0 comments posted 19yrs

posted by emu

0 comments posted 19yrs posted by emu

SETUP & HOLD time confusion

In the Xilinx Synthesis and Simulation Design Guide there is this phrase: "While Xilinx data sheets report that there a...

11 comments posted 19yrs

posted by mhs000

11 comments posted 19yrs posted by mhs000

XPS behavioral simulation fails: the design is not loaded

After designing a peripheral and checking that it is working with the BFM simulation, I am trying to simulate the whole...

4 comments posted 19yrs

posted by le_marq

4 comments posted 19yrs posted by le_marq

Problem with EDK 8.2 MicroBlaze Tutorial

I am trying to work through the "EDK 8.2 MicroBlaze Tutorial in Spartin 3" When I get to the point of "Generate Program...

0 comments posted 19yrs

posted by scot.willis

0 comments posted 19yrs posted by scot.willis

Changing LUT input size in synthesize

Dear all, I'm doing research on FPGA's LUT input size. And i'm using synplify pro to synthesize vhdl/verilog to edf for...

1 comments posted 19yrs

posted by yuchiwai

1 comments posted 19yrs posted by yuchiwai

EDK + XMD

Hi, Here is my problem. My memory map is as follows: ISBRAM : 0xFFFFE000:0xFFFFFFFF SDRAM : = 0xF0000000:0xF1FFFFFF I d...

1 comments posted 19yrs

posted by eascheiber

1 comments posted 19yrs posted by eascheiber

how two sine signals are multiplied in VHDL language

hi all, iam doing projevt on Digital down converter.In that i need to multiply RF signal and LO signal . which type of...

2 comments posted 19yrs

posted by kanthi.siddela

2 comments posted 19yrs posted by kanthi.siddela

Which are the best books about CORDIC algorithms and applications

Hi, I want to buy two books on CORDIC. One is focused on CORDIC theory and algorithms, another on CORDIC applications....

15 comments posted 19yrs

posted by wtxwtx

15 comments posted 19yrs posted by wtxwtx

XST and Verilog $readmemh

In theory, XST claims to support the Verilog $readmemh to initialize memory. I'm using the latest 9.x s/w verion. I loo...

1 comments posted 19yrs

posted by johnp3+nospam

1 comments posted 19yrs posted by johnp3+nospam

Timing violations though constraints have been met

I keep on getting Setup time violations from ModelSim despite the fact that my design successfully placed and routed wi...

3 comments posted 19yrs

posted by mhs000

3 comments posted 19yrs posted by mhs000

ispLever 6.1 complains about missing libc.so.6 on Gentoo 2006.1

Evnin' Just received the ispLever Linux DVD today... Install went fine...but when setting up environment or trying to s...

1 comments posted 19yrs

posted by Jedi Router

1 comments posted 19yrs posted by Jedi Router

lwIP, temac, and DMA

The documentation for the lwIP core (v2.00a) shows that there's only support for FIFO data transfers when using the TEM...

0 comments posted 19yrs

posted by kunals.spam.account

0 comments posted 19yrs posted by kunals.spam.account