Due to RAM access, I calculate data on rising edge while feed into the RAM on negedge edge of clk_100m_i, which is 100MHz. To me, the delay between my_data and latching into ram_data is 15ns, while ISE may treat it as 5ns..
reg [3:0] my_stages; reg [31:0] my_data;
always @(posedge clk_100m_i or negedge rst) if (!rst) ... else begin // one-hot shift register my_stages