How do I constrain Xilinx to implement multi-cycle paths?

Due to RAM access, I calculate data on rising edge while feed into the RAM on negedge edge of clk_100m_i, which is 100MHz. To me, the delay between my_data and latching into ram_data is 15ns, while ISE may treat it as 5ns..

reg [3:0] my_stages; reg [31:0] my_data;

always @(posedge clk_100m_i or negedge rst) if (!rst) ... else begin // one-hot shift register my_stages

Reply to
news reader
Loading thread data ...

Dear Mr. Reader Read the manual? :-) I suggest you start with the Constraints Guide. Search for 'multi cycle'. HTH, Syms.

Reply to
Symon

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.