Field-Programmable Gate Arrays

POC at Element CXI

Does anyone know of a good point of contact at Element CXI? I am currently doing an evaluation of potential platforms /...

2 comments posted 19yrs

posted by anneatkinson

2 comments posted 19yrs posted by anneatkinson

has anyone used mathstar field programmable object arrays?

Just wondered if anyone here has used these devices... I want to do embedded computer vision applications and it sounds...

3 comments posted 19yrs

posted by wallge

3 comments posted 19yrs posted by wallge

Wanted: XUP Virtex II Pro DDR-controller

Hello I need to create a dual port ram from my DDR-RAM from within hardware. But I can't figure out how to make it work...

0 comments posted 19yrs

posted by wouter.vanhauwaert

0 comments posted 19yrs posted by wouter.vanhauwaert

Help!! FIR Polyphase second - order interpolator

i need a efficent FIR Polyphase second - order interpolator code i want to use it on Cyclone II .Plese help me ,Thank yo...

1 comments posted 19yrs

posted by kangwei365

1 comments posted 19yrs posted by kangwei365

FIFO newbie question

Hi all, I'm designing a small project which uses the primitive FIFO_16 of virtex 4. The problem is: This FIFO uses an a...

4 comments posted 19yrs

posted by mazouz.nezhate

4 comments posted 19yrs posted by mazouz.nezhate

Query in Parallel CRC(urgent)

Hi, Can anyone plz tell me the theory behind 32bit parallel CRC? i m not getting the basis on which the 32 bit CRC is b...

2 comments posted 19yrs

posted by pra.vlsi

2 comments posted 19yrs posted by pra.vlsi

Please HELP: timing problems on Virtex-4FX

Hello, I am working with the ML410 board and the V4FX60 FPGA. For the past week and a half, I've been having problems m...

5 comments posted 19yrs

posted by Dmitriy.Bekker

5 comments posted 19yrs posted by Dmitriy.Bekker

Xilinx WebCase support

I have a webcase open since 3/20. Though I have been given decent support I find that I get one and only one email from...

7 comments posted 19yrs

posted by mottoblatto

7 comments posted 19yrs posted by mottoblatto

CPLD + µC with reasonably-priced tools?

Hi all, I have a potential (hobby) project, where I'm looking at needing, in effect, a CPLD and a µC that can share mem...

12 comments posted 19yrs

posted by hpa

12 comments posted 19yrs posted by hpa

Flip Flop problem (asynchronous or synchronous???? )

Hi everybody, i have a missunderstanding of the flip flop behavior: usually the output of a flip flop is assigned its i...

9 comments posted 19yrs

posted by Amine.Miled

9 comments posted 19yrs posted by Amine.Miled

Problème de bascues (asynchrone ou synchrone?)

Salut, il y a un ph=E9nom=E8ne =E9trange que je n'arrive pas =E0 comprendre: normalement lorsqu'on consoit une bascule...

2 comments posted 19yrs

posted by Amine.Miled

2 comments posted 19yrs posted by Amine.Miled

EDK 8.2 MicroBlaze Tutorial

I am trying to work through the "EDK 8.2 MicorBlaxe Tutorial in Spartin 3" When I get to the point of "Generate Program...

0 comments posted 19yrs

posted by scot.willis

0 comments posted 19yrs posted by scot.willis

Available: Detailed RISC CPU IP Core Design Documentation

Hello, I have put up an article on our web site that describes a RISC CPU IP Core that was created for one of our clien...

0 comments posted 19yrs

posted by no

0 comments posted 19yrs posted by no

System Generator pcore I/O performance results

Hello all: I have a question regarding using SysGen to create a co-processor that's used in a microblaze design. I'm us...

7 comments posted 19yrs

posted by wilder_joel

7 comments posted 19yrs posted by wilder_joel

Ross Freeman - inventor of the FPGA

I understand that the inventor of the FPGA was a Ross Freeman, who died aged 45, tragically just 5 years after he co-cou...

5 comments posted 19yrs

posted by fancier.fpga

5 comments posted 19yrs posted by fancier.fpga