Timing violations though constraints have been met

I keep on getting Setup time violations from ModelSim despite the fact that my design successfully placed and routed within the given time constraint. Can anybody suggest a reason for that or a work around? I assume that I do not need to constraint the specific paths causing the violation since the clock period constraint should be global for all paths.

Thank you.

Reply to
M. Hamed
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If that place + route met static timing, I would expect that the design is OK.

-- Mike Treseler

Reply to
Mike Treseler

It isn't clear in your post but I guess you are doing a post place and route simulation. A typical mistake is to instantiate a post place and route netlist from a testbench which was never intended to be connected to such a netlist. An example:

mynetlist dut(.clk(clk),.signalA(signalA), ... ); always @(posedge clk) signalA

Reply to
Andreas Ehliar

Correct. I'm doing a post-place and route simulation. My testbench only provides clock and reset to the module but there are a number of modules that simulate external components. All the inputs from these componenets are latched first and sampled on the internal clock. Some of them are asynchronously latched though which I suspect maybe part of the problem.

I also traced some of the timing violations to two inferred latches that I thought harmless (never again). I was just wondering if the static timing analyzer calculates the timing paths length from a latch output rather than its driving flip-flop output?!

Thanks for the suggestions


Reply to
M. Hamed

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