Dear all, I'm doing research on FPGA's LUT input size. And i'm using synplify pro to synthesize vhdl/verilog to edf for virtex2 device. Do you know how to limit the LUT input size to 1, 2,3 in synplify pro?
And even, could I use 5,6,7,8 .... -input LUT in synplify pro (also using virtex2 device).
Many thanks for your help !
Regards, Yu