Latest threads in Field-Programmable Gate Arrays

Is anyone has experience to share OPB for 2 PowerPC in MPMC2 core

It seems there is problem with OPB in MPMC2 core. PPC will dead when 2 PPC share OPB peripherals in MPMC2 core

1 19yrs

johnsuner

1 19yrs johnsuner

FPGA and DAC for wave generation

hi..I'm a university student familiar with the only the basics of VHDL and FPGA implementation..For my project, I'm try...

4 19yrs

sheetalgandhi333

4 19yrs sheetalgandhi333

How to add customer peripheral with IP core to EDK?

Hi All, I am trying to add a customized OPB peripheral to the Microblaze system in EDK/Platform Studio 8.1. My peripher...

1 19yrs

espzzh

1 19yrs espzzh

I make a usb blaster for altera by myself!

it is work good!

2 19yrs

cppcpldfpga

2 19yrs cppcpldfpga

Take verilog code from Xilinx Core generator

Hi everyone! I use Xilinx Core generator to generate DA FIR filter. Right now, I want to take the verilog code for DA FI...

7 19yrs

gordonfreeman1983

7 19yrs gordonfreeman1983

XTREME DSP Development Kit2 JTAG Problem

Hi all, I m using the Xtreme DSP Development Kit 2 with Viretex 2 XC2V3000-4FG676 FPGA. While doing JTAG cosimulation i...

1 19yrs

sfoo

1 19yrs sfoo

Slave PLB core interrupt

Hello, Just finished writing an ADC driver which I connected to a PPC via PLB (slave configuration). I have also instan...

2 19yrs

mloulah

2 19yrs mloulah

I/O-Standards: HSTL vs. SSTL and others...

Hello all, my question - I/O-Standards - I have searched the WWW up and down, but I'm really not happy what I have foun...

1 19yrs

WeikEngOff

1 19yrs WeikEngOff

free architecture

This it is a message of Richard Staman creator of free softeare fundation and GNU on an idea to construct free hardware...

2 19yrs

jrquevedor

2 19yrs jrquevedor

V5 GTP question

I have an application where I need to use 20 V5 GTPs each running at 3.2 Gbps to trasmit data out to a source synchrono...

6 19yrs

cpandya

6 19yrs cpandya

Problem with real data type

I am using using the Xilinx project navigator Version 6.2i for writing the VHDL code and synthesize it .I am facing a p...

5 19yrs

sankpalhrishi

5 19yrs sankpalhrishi

Non-intrusive readback on FPGA configuration data

Hello, I was wondering if anyone knows if it's possible to perform a "non- intrusive" readback operation on the FPGA co...

3 19yrs

sumeet.abrol

3 19yrs sumeet.abrol

DONE problems

Hi, I am having a problem with a design. When DONE cycle is set to 5 or 6 DONE pin never goes high. I have confirmed th...

4 19yrs

ddallen

4 19yrs ddallen

VHDL editing with UltraEdit

Hello, I decided to test UltraEdit to see how good is it in reformatting a VHDL code and indenting smartly. To do this...

14 19yrs

(myname_here)_123456

14 19yrs (myname_here)_123456

Lattice pricing

Good morning (o; Lattice Semiconductor has given up their website' (o; Anyway...I just wanted to ask what are the appro...

1 19yrs

me

1 19yrs me

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