Field-Programmable Gate Arrays

How to add customer peripheral with IP core to EDK?

Hi All, I am trying to add a customized OPB peripheral to the Microblaze system in EDK/Platform Studio 8.1. My peripher...

1 comments posted 19yrs

posted by espzzh

1 comments posted 19yrs posted by espzzh

I make a usb blaster for altera by myself!

it is work good!

2 comments posted 19yrs

posted by cppcpldfpga

2 comments posted 19yrs posted by cppcpldfpga

Take verilog code from Xilinx Core generator

Hi everyone! I use Xilinx Core generator to generate DA FIR filter. Right now, I want to take the verilog code for DA FI...

7 comments posted 19yrs

posted by gordonfreeman1983

7 comments posted 19yrs posted by gordonfreeman1983

XTREME DSP Development Kit2 JTAG Problem

Hi all, I m using the Xtreme DSP Development Kit 2 with Viretex 2 XC2V3000-4FG676 FPGA. While doing JTAG cosimulation i...

1 comments posted 19yrs

posted by sfoo

1 comments posted 19yrs posted by sfoo

Slave PLB core interrupt

Hello, Just finished writing an ADC driver which I connected to a PPC via PLB (slave configuration). I have also instan...

2 comments posted 19yrs

posted by mloulah

2 comments posted 19yrs posted by mloulah

I/O-Standards: HSTL vs. SSTL and others...

Hello all, my question - I/O-Standards - I have searched the WWW up and down, but I'm really not happy what I have foun...

1 comments posted 19yrs

posted by WeikEngOff

1 comments posted 19yrs posted by WeikEngOff

free architecture

This it is a message of Richard Staman creator of free softeare fundation and GNU on an idea to construct free hardware...

2 comments posted 19yrs

posted by jrquevedor

2 comments posted 19yrs posted by jrquevedor

V5 GTP question

I have an application where I need to use 20 V5 GTPs each running at 3.2 Gbps to trasmit data out to a source synchrono...

6 comments posted 19yrs

posted by cpandya

6 comments posted 19yrs posted by cpandya

Problem with real data type

I am using using the Xilinx project navigator Version 6.2i for writing the VHDL code and synthesize it .I am facing a p...

5 comments posted 19yrs

posted by sankpalhrishi

5 comments posted 19yrs posted by sankpalhrishi

Non-intrusive readback on FPGA configuration data

Hello, I was wondering if anyone knows if it's possible to perform a "non- intrusive" readback operation on the FPGA co...

3 comments posted 19yrs

posted by sumeet.abrol

3 comments posted 19yrs posted by sumeet.abrol

DONE problems

Hi, I am having a problem with a design. When DONE cycle is set to 5 or 6 DONE pin never goes high. I have confirmed th...

4 comments posted 19yrs

posted by ddallen

4 comments posted 19yrs posted by ddallen

VHDL editing with UltraEdit

Hello, I decided to test UltraEdit to see how good is it in reformatting a VHDL code and indenting smartly. To do this...

14 comments posted 19yrs

posted by (myname_here)_123456

14 comments posted 19yrs posted by (myname_here)_123456

Lattice pricing

Good morning (o; Lattice Semiconductor has given up their website' (o; Anyway...I just wanted to ask what are the appro...

1 comments posted 19yrs

posted by me

1 comments posted 19yrs posted by me

Symbol names in the Design Hierarchy Window of the Xilinx Floorplanner

I am trying to analyze amount of the FPGA (V4) resources used by each of my hierarchical blocks. I am not sure if there...

2 comments posted 19yrs

posted by mbmsv

2 comments posted 19yrs posted by mbmsv

Raggedstone1 LVDS Oscillator

For those of you that have been waiting for this module the LVDS oscillator module for our low cost Spartan-3 Raggedsto...

0 comments posted 19yrs

posted by g1

0 comments posted 19yrs posted by g1