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FPGA and DAC for wave generation

hi..I'm a university student familiar with the only the basics of VHDL and FPGA implementation..For my project, I'm trying a make a sine wave, ramp, triangular and square wave generator which outputs required wave of required amplitude and required frequency

The FPGA is connected with DAC thru I2C bus..

The development board (nanoboard) has on- board freq of 20 mhz...now the dac being connected to the I2c bus can work upto max 400 Mhz..so a suitable clock divisor has to be implemented ..thus a low frequency can be used as SCL input to DAC..

a)Now, for the sine and square wave, I'm assuming that we can use the same look-up table(values ranging from 0 to 256)for the output values of DAC.for obtaining different frequencies, only the SCL needs to be changed . i.e.if SCl rate is high, the DAC would output from 0 to 256, then to 0 at a faster rate, if SCL is low, it would output the same values, but with some delay. THus, variable frequency can be obtained by changing SCL rate..am I correct in assuming so?

b)If this is correct, can anyone please tell me the relationship between SCL and output wave frequency..if such a formula/well defined relationship does exist

c) Also, can anyone tell me about a good link for a simple tutorial on implementing look-up table?I did find some on the web, but they all seemed to be complicated..either because they ARE..or because my mind has gone all-blank right now, with the submission date coming so near..

Any help at this time would be hugely appreciated

Kind Regards, Sheetal Gandhi

Reply to
Sheetal
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That's going to be slow. Are you sure that is the data interface, and not a secondary control interface?

You could. But your frequency resolution would be limited to only those frequencies which are factors of your clock rate divided by your table lenght. In some applications that is fine, in others it would be unacceptable.

For finer frequency resolution, what is typically done is to have a wide phase accumulator register - maybe 40 bits but depending on the application. Each clock cycle, you add a value computed from the frequency to the phase register. At high frequencies it will increment more each step, at low frequencies it will increment less. Then you take only some of the top bits - lets say maybe the 12 most significant bits - and use them as the address into your lookup table. This means that while the phase of the output samples will jitter around a bit, the actual frequency can be adjusted with very high accuracy and fine resolution. If you put an analog low-pass filter on the output of your DAC, you can make some very nice sine waves.

Reply to
cs_posting

400 KHz, i hope. This means you're not going to get very high frequencies on your output, but you must realize that already...

This is one way to do it, but not how it is generally done. Realizing that your I2C update rate is on the order of 1/20th of the SCL frequency already, making the update rate slower will even further limit your output quality due to lower update rate. In a typical waveform generator, the data is sent to the DAC at the highest frequency possible. This reduces output filtering requirements. Changes in output frequency and waveform are made by altering the increment added to the table index on each DAC update.

This depends on the DAC you're using. Most I2C devices are written by sending a 7-bit address plus write bit followed by an

8 bit value for a simple device (one internal register) or two 8-bit values (internal address followed by data) for multi- register devices. Additional cycles (always another 8-bit word at a time) may be required if the value you're writing is more than 8 bits (e.g. 12-bit DAC needs at least two data writes plus any address and "subaddress" bytes).

In any case SCL will not be free-running (take a look at the I2C spec or the DAC device datasheet). So you'll have some additional time to generate start and stop conditions on the bus. Some very simple DAC devices may allow you to write continuously after startup. Again you'll need to check your device's datasheet.

So now you've got some frequency that you can update the DAC in the low 10's of KHz rate at best. Your output wave frequency will then depend on how many table look-ups you do per complete waveform. As I said earlier, it is the latter that normally changes the frequency in a typical waveform generator. i.e. you may have a 128 word waveform table. So to get a frequency of 1/128 of the DAC update frequency you'd increment the table index by 1 on each update. Increasing the index increment will increase the frequency. It is also possible to increment the index by a non-integer amount (with or without table interpolation depending on requirements for output accuracy).

HTH, Gabor

Reply to
Gabor

To generate programmable frequencies in an FPGA, use Direct Digital Synthesis (DDS) Look it up in google. Driving the DAC through an I2C bus seems to be unnecessarily slow. If your FPGA has BlockRAMs, then look-up tables are very easy to implement.

You did not menti> hi..I'm a university student familiar with the only the basics of VHDL

Reply to
Peter Alfke

Tip: Some tutors will mark incorrect units wrong, so take care on these. m=milli, and M-Mega, and check when you write MHz that is what you mean.

Broadly speaking, yes.

Read the data sheet on the DAC. Each DAC update will take an i2c frame, of a number of clocks [address.data]

How hard can a table be - you can draw a Graph, and use XCELL ? Tip: For table compression, it is common to fold the table, so for a sine wave, how much of the whole sine cycle, do you actually need to store ?

I'd look for a SPI DAC, as it seems silly to constrain the MAX clock speed of a design, by the i2c MAX - SPI DACs can run closer to the FPGA speeds.

-jg

Reply to
-jg

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