Field-Programmable Gate Arrays

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simulating with OSe 9.1.3

Hello, I am new in FPGA. I am using ISE 9.1.3 on windows. I wrote some VHDL codes and when I run the simulation ( from...
0 comments posted 19yrs
posted by (myname_here)_123456
0 comments posted 19yrs posted by (myname_here)_123456

Memory generator IP core ISE Webpack

Greetings... I have been trying to use a block memory component (in this case just a single port ROM to start with... w...
0 comments posted 19yrs
posted by thesteveman_ice9
0 comments posted 19yrs posted by thesteveman_ice9

Ouputs during startup and Programming

Hi, I have designed a motor controller with the Virtex 4 FX-12 Mini-Module and I of course would like the PWM output pi...
8 comments posted 19yrs
posted by RobotBuilder
8 comments posted 19yrs posted by RobotBuilder

Question about intalling EDK9.1i

Hello, I intalled the ISE9.1i and updated it. It can work. Then I installed EDK9.1i. But when I run it, it told me "The...
0 comments posted 19yrs
posted by pang.dudu.pang
0 comments posted 19yrs posted by pang.dudu.pang

Looking for a spartan 3 board

I'm looking for a (low-cost) spartan 3 based board, containing a low to medium sized spartan 3 fpga, two 100 MSPS 12 bi...
3 comments posted 19yrs
posted by theller
3 comments posted 19yrs posted by theller

FPGA Newbie

Hey Guys/Gals, I'm only fairly new to FPGA's, I've used the xilinx xc2s400e, but this was on a digilent board and the w...
13 comments posted 19yrs
posted by mafroew
13 comments posted 19yrs posted by mafroew

FPGA MAC for Point to Point Connection

Hi everyone, I've been reading previous posts regarding ethernet MAC layers for FPGA's but can't seem to solve my probl...
0 comments posted 19yrs
posted by meo2662
0 comments posted 19yrs posted by meo2662

Stratix II - Cyclone II GATE COUNT

Hi, Is there an Altera application to count the number of equivalent gates for Logic Elements, Memory, DSP blocks, PLL e...
2 comments posted 19yrs
posted by vhdldesigner.patrick
2 comments posted 19yrs posted by vhdldesigner.patrick

FPGA Full Custum Design

Hi all, I am developing my first FPGA LUT-Based design.Trying to make a FPGA with MRAM based design. There is anyone her...
1 comments posted 19yrs
posted by mourad.elbaraji
1 comments posted 19yrs posted by mourad.elbaraji

Clock signal FPGA XC95288xl144

Hi All, I have problem with clock signal in FGPA XC95288XL144. I have 3,3V signal on the output but I want get 5V signa...
2 comments posted 19yrs
posted by maroni
2 comments posted 19yrs posted by maroni

DARNAW! - PGA Style FPGA Module

Finally first picture of Darnaw1 our PGA style FPGA board is here here http://www.enterpoint.co.uk/moelbryn/darnaw1.htm...
14 comments posted 19yrs
posted by g1
14 comments posted 19yrs posted by g1

questions about pci conmmunications on a pcb board

Hi, A PCB has been designed to faciliate communications between Virtex4 FPGA and an infiniband(ib) chip. The v4 fpga ha...
0 comments posted 19yrs
posted by lipeng.net
0 comments posted 19yrs posted by lipeng.net

Free Hardware

This it is a message of Richard Staman creator of free softeare fundation and GNU on an idea to construct free hardware...
27 comments posted 19yrs
posted by jrquevedor
27 comments posted 19yrs posted by jrquevedor

xilprofile for edk 8.2

Hi All, After searching the web (and xilinx's own site) for any references to the "xilprofile" library or documentation...
1 comments posted 19yrs
posted by PaddyDempster
1 comments posted 19yrs posted by PaddyDempster