Latest threads in Field-Programmable Gate Arrays

OPB master and slave interface for DDR SDRAM controller

Hi, I am almost new in google gruops. I build IPIF master to control OPB DDR SDRAM controller. Using Create/Import Peri...

0 19yrs

shineby

0 19yrs shineby

Using OPB PCI In EDK 8.1

(This is my third attempt to send the same post to the group. The previous two posts still have not appeared on the gro...

0 19yrs

sheikh.m.farhan

0 19yrs sheikh.m.farhan

physical chip size

Dear I am looking at data book of Xilinx Virtex-II Pro to find ACTUAL CHIP SIZE. So far, I could not find yet -: (as an...

10 19yrs

pasacco

10 19yrs pasacco

Virtex-5 FX when ? (II)

Hello Antti, Peter and ..., yep, some months later now - the same question... V5-FX? Thanks and greetings Udo

2 19yrs

WeikEngOff

2 19yrs WeikEngOff

Image compression on FPGA

Hello, i'd like to have some informations about image compression on FPGA hardware. Do you have some experiences with t...

2 19yrs

erixx

2 19yrs erixx

Using OPB PCI Bridge in EDK 8.2i

Hi, I have been trying to use the OPB PCI bridge in EDK 8.2. So far I have not been able to synthesize it properly. I a...

0 19yrs

sheikh.m.farhan

0 19yrs sheikh.m.farhan

Using PCI in EDK 8.21

Hi, I have been trying to use the OPB PCI bridge in EDK 8.2. So far I have not been able to synthesize it properly. I a...

0 19yrs

sheikh.m.farhan

0 19yrs sheikh.m.farhan

Incorrect response from MAC FIR Low Pass Filter

Hi all, thanks to your help, I have managed to solve the JTAG problem on my XTREME DSP Development Kit. However I had a...

2 19yrs

sfoo

2 19yrs sfoo

compact flash slave ip core

Where can I find the compact flash slave ip core for free,thanks!

0 19yrs

bjzhangwn

0 19yrs bjzhangwn

XPS and inout ports: is it possible?

Hi, Im woerking on a Xilinx Virtex-II pro with Xilinx Platform Studio 7.1 My design has a bidirectional 8-bits bus. If...

0 19yrs

ibonesana

0 19yrs ibonesana

Problem with PowerPC PIT interrupt

I'm working on a RTOS for the PowerPC chip on the Virtex-II XUP board. I need an interrupt to trigger so I run my sched...

7 19yrs

mdhicks2

7 19yrs mdhicks2

The simulation library compilation wizard of EDK can't find modelsim

Hi, All: When I complie the simulation library in EDK 9.1.01i using the library compilation wizard, it told me that "mo...

4 19yrs

pang.dudu.pang

4 19yrs pang.dudu.pang

EDK Simulation library compilation wizard can't find modelsim

Hello, I am using the Simulation library compilation wizard in EDK9.1.01i and was told that "Modlelsim isn't found! ple...

2 19yrs

pang.dudu.pang

2 19yrs pang.dudu.pang

Altera DPA compatible with Xilinx IOSERDES?

Has anyone had success interfacing Altera DPA with Xilinx ISERDES/OSERDES/IDELAY? Is 1 Gb/s/pin feasible for Virtex-5 a...

0 19yrs

jhallen

0 19yrs jhallen

Increase memory resource at Xil_malloc.

Hi, I have to write a program with threads and when I reserve memory for these threads, an error occurs if this memory...

0 19yrs

pbantunez

0 19yrs pbantunez

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