Field-Programmable Gate Arrays

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physical chip size

Dear I am looking at data book of Xilinx Virtex-II Pro to find ACTUAL CHIP SIZE. So far, I could not find yet -: (as an...
10 comments posted 19yrs
posted by pasacco
10 comments posted 19yrs posted by pasacco

Virtex-5 FX when ? (II)

Hello Antti, Peter and ..., yep, some months later now - the same question... V5-FX? Thanks and greetings Udo
2 comments posted 19yrs
posted by WeikEngOff
2 comments posted 19yrs posted by WeikEngOff

Image compression on FPGA

Hello, i'd like to have some informations about image compression on FPGA hardware. Do you have some experiences with t...
2 comments posted 19yrs
posted by erixx
2 comments posted 19yrs posted by erixx

Using OPB PCI Bridge in EDK 8.2i

Hi, I have been trying to use the OPB PCI bridge in EDK 8.2. So far I have not been able to synthesize it properly. I a...
0 comments posted 19yrs
posted by sheikh.m.farhan
0 comments posted 19yrs posted by sheikh.m.farhan

Using PCI in EDK 8.21

Hi, I have been trying to use the OPB PCI bridge in EDK 8.2. So far I have not been able to synthesize it properly. I a...
0 comments posted 19yrs
posted by sheikh.m.farhan
0 comments posted 19yrs posted by sheikh.m.farhan

Incorrect response from MAC FIR Low Pass Filter

Hi all, thanks to your help, I have managed to solve the JTAG problem on my XTREME DSP Development Kit. However I had a...
2 comments posted 19yrs
posted by sfoo
2 comments posted 19yrs posted by sfoo

compact flash slave ip core

Where can I find the compact flash slave ip core for free,thanks!
0 comments posted 19yrs
posted by bjzhangwn
0 comments posted 19yrs posted by bjzhangwn

XPS and inout ports: is it possible?

Hi, Im woerking on a Xilinx Virtex-II pro with Xilinx Platform Studio 7.1 My design has a bidirectional 8-bits bus. If...
0 comments posted 19yrs
posted by ibonesana
0 comments posted 19yrs posted by ibonesana

Problem with PowerPC PIT interrupt

I'm working on a RTOS for the PowerPC chip on the Virtex-II XUP board. I need an interrupt to trigger so I run my sched...
7 comments posted 19yrs
posted by mdhicks2
7 comments posted 19yrs posted by mdhicks2

Altera DPA compatible with Xilinx IOSERDES?

Has anyone had success interfacing Altera DPA with Xilinx ISERDES/OSERDES/IDELAY? Is 1 Gb/s/pin feasible for Virtex-5 a...
0 comments posted 19yrs
posted by jhallen
0 comments posted 19yrs posted by jhallen

Increase memory resource at Xil_malloc.

Hi, I have to write a program with threads and when I reserve memory for these threads, an error occurs if this memory...
0 comments posted 19yrs
posted by pbantunez
0 comments posted 19yrs posted by pbantunez

FPGA and DAC for wave generation

hi..I'm a university student familiar with the only the basics of VHDL and FPGA implementation..For my project, I'm try...
4 comments posted 19yrs
posted by sheetalgandhi333
4 comments posted 19yrs posted by sheetalgandhi333