physical chip size

Hi

Can we know actual DIE size ? For example, V2P100-ff1704

As far as I find, data book does not contain the information.

I need chip (that we see in the FPGA EDITOR) size -:.

Can anyone help me? Should I ask Xilinx?

You make a rough guestimate yourself. The largest FPGA in a given technology will be the size of one reticle (500mm^2 to 900mm^2 depending on technology). From there the size should scale down roughly linearly in the number of CLBs.

Kolja Sulimma

Hello

For research work,

my goal is to estimate the ASIC-equivalent AREA in terms of [um^2]

of my design implemented in Virtex-II Pro.

As an example, V2P30 implementation is that

I am trying to approxiate

"LUT utilization" x "Die size" (1)

or

"Individual LUT physical size" x "Number of utilized LUTs" (2)

as an ASIC-equivalent AREA.

Equation (1) is over-simplification.

Equation (2) is not considering wire utilization and other logic utilization.

I need comment from experienced one.

Thank you in advance.

For what final purpose ? - there will be considerable elasticity in the answer, and it has little practical relevance, as you do not buy either device by the Acre.

Still, you can get ballparks without too much effort : Find the smallest package the largest FPGA in your series is offered in, and the die area must be less than that :) [ but probably not a lot less ]

Or, get your hands on a dead device, and open it up. Die area is easy to see.

If you want a more useful ASIC metric, take a known Industry IP block and the usage in that same FPGA, and then look at the cost of that as a Std high volume chip.

-jg

Hi

I found one article in FPGA 2006 conference.

They calculated "number of logic blocks" x "area of each block".

They state that the area ratio is around 33 for logic, for a number of benchmarks.

Then probably I also need information on LUT (or slice) actual size.

If anyone knows how to obtain this information, let me know.

Thank you in advance.

Why don't you synthesize to an ASIC directly? I am sure that your university has access to a commercial synthesis tool like design compiler. But there are also some free academic tools available. Than you can choose a technology and the tool will tell you the chip area for your design. Cell libraries for some technologies are availale on line for free, for others you need to sign an NDA with eurochip or mosis.

Kolja Sulimma

Any such numbers are useful only for very rough guesstimates.

Many constructs like multiplexers can be implemented as extremely compact and fast wired-OR instead of FPGA-style cascaded 2:1/4:1 LUT multiplexers. Other components like memories sit at the other end of the spectrum with nearly 1:1 correspondence.

One design may have a 33:1 FPGA:ASIC ratio, another may be over 40:1 and yet another may be below 20:1... it all really depends on how the logic was designed, how it got synthesized, what resources were available to map the design onto, etc. Results WILL vary CONSIDERABLY depending on several design/tool/etc.-specific details, many of which may be beyond your (or anybody else's for that matter) control.