Hi, I have been trying to use the OPB PCI bridge in EDK 8.2. So far I have not been able to synthesize it properly. I am using a custom board with Virtex II, I include the PCI bridge during the BSB wizard. Is the assembly view, I configure the IP to be used as a target. My first milestone is to put PCI target on an FPGA board withe the PCI edge connector, put it in a PC and the PC should detect the PCI board. I need to have the PCI target to be configured from the PC side. Now my questions are:
- When I set all the configurations for the PCI to be used as a target, why dont I see the IDSEL line in my ucf file?
- In the generated ucf, I see two clocks with the name PCI_CLK_FB and PCI_CLK_OUT. After digging, I came to know that these clocks make more sense when the PCI bridge is to be used as a host (on a mothernboard as is used in ML310 board) where PCI_CLK_OUT is the source PCI clock and PCI_CLK_FB is the feedback clock. AFter consulting some more MHS files from the reference designs, I do see the PCLK appearing in the ucf and MHS file (instead of PCI_CLK_FB and PCI_CLK_OUT clocks). When I set the PCI bridge as a target (by setting C_INCLUDE_OPB_MST2PCI_TARG = 0), I dont see any IDSEL line appearing in my ucf, why is that so?
- Synthesizing the project as it is, without the IDSEL line available at the ports, I start getting NgdBuild errors on ilmb_BE line to be driven by mulitple sources. I am pasting the MHS file. Kindly guide how to achieve the first milestone.
Farhan
# ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4 # Tue Apr 24 17:00:33 2007 # Target Board: Custom # Family: virtex2 # Device: xc2v1000 # Package: fg456 # Speed Grade: -4 # Processor: Microblaze # System clock frequency: 40.000000 MHz # Debug interface: On-Chip HW Debug Module # On Chip Memory : 8 KB # ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_PCI_Bridge_PAR = fpga_0_PCI_Bridge_PAR, DIR = IO PORT fpga_0_PCI_Bridge_PERR_N = fpga_0_PCI_Bridge_PERR_N, DIR = IO PORT fpga_0_PCI_Bridge_SERR_N = fpga_0_PCI_Bridge_SERR_N, DIR = IO PORT fpga_0_PCI_Bridge_IRDY_N = fpga_0_PCI_Bridge_IRDY_N, DIR = IO PORT fpga_0_PCI_Bridge_FRAME_N = fpga_0_PCI_Bridge_FRAME_N, DIR = IO PORT fpga_0_PCI_Bridge_DEVSEL_N = fpga_0_PCI_Bridge_DEVSEL_N, DIR = IO PORT fpga_0_PCI_Bridge_STOP_N = fpga_0_PCI_Bridge_STOP_N, DIR = IO PORT fpga_0_PCI_Bridge_TRDY_N = fpga_0_PCI_Bridge_TRDY_N, DIR = IO PORT fpga_0_PCI_Bridge_AD = fpga_0_PCI_Bridge_AD, DIR = IO, VEC = [31:0] PORT fpga_0_PCI_Bridge_CBE = fpga_0_PCI_Bridge_CBE, DIR = IO, VEC = [3:0] PORT fpga_0_PCI_CLK_FB = pci_feedback_s, DIR = I, SIGIS = CLK PORT fpga_0_PCI_CLK_OUT = pci_clk_s, DIR = O PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =
40000000 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RSTBEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 5.00.c PARAMETER C_USE_FPU = 0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_NUMBER_OF_PC_BRK = 2 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DOPB = mb_opb BUS_INTERFACE IOPB = mb_opb PORT DBG_CAPTURE = DBG_CAPTURE_s PORT DBG_CLK = DBG_CLK_s PORT DBG_REG_EN = DBG_REG_EN_s PORT DBG_TDI = DBG_TDI_s PORT DBG_TDO = DBG_TDO_s PORT DBG_UPDATE = DBG_UPDATE_s END
BEGIN opb_v20 PARAMETER INSTANCE = mb_opb PARAMETER HW_VER = 1.10.c PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_rst_s PORT OPB_Clk = sys_clk_s END
BEGIN opb_mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 2.00.a PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0x41400000 PARAMETER C_HIGHADDR = 0x4140ffff BUS_INTERFACE SOPB = mb_opb PORT DBG_CAPTURE_0 = DBG_CAPTURE_s PORT DBG_CLK_0 = DBG_CLK_s PORT DBG_REG_EN_0 = DBG_REG_EN_s PORT DBG_TDI_0 = DBG_TDI_s PORT DBG_TDO_0 = DBG_TDO_s PORT DBG_UPDATE_0 = DBG_UPDATE_s END
BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_rst_s PORT LMB_Clk = sys_clk_s END
BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_rst_s PORT LMB_Clk = sys_clk_s END
BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_port END
BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_port END
BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = ilmb_port BUS_INTERFACE PORTB = dlmb_port END
BEGIN opb_pci PARAMETER INSTANCE = PCI_Bridge PARAMETER HW_VER = 1.02.a PARAMETER C_DMA_CHAN_TYPE = 0 PARAMETER C_INCLUDE_INTR_MODULE = 0 PARAMETER C_PCIBAR_NUM = 2 PARAMETER C_TRIG_PCI_READ_OCC_LEVEL = 8 PARAMETER C_TRIG_IPIF_WRBURST_OCC_LEVEL = 8 PARAMETER C_TRIG_PCI_DATA_XFER_OCC_LEVEL = 8 PARAMETER C_INHIBIT_IPIF_READ_VAC_LEVEL = 8 PARAMETER C_TRIG_IPIF_READ_OCC_LEVEL = 8 PARAMETER C_NUM_PCI_RETRIES_IN_WRITES = 15 PARAMETER C_NUM_PCI_PRDS_BETWN_RETRIES_IN_WRITES = 15 PARAMETER C_MAX_LAT = 0x54 PARAMETER C_MIN_GNT = 0x32 PARAMETER C_NUM_IDSEL = 1 PARAMETER C_DMA_LENGTH_WIDTH = 11 PARAMETER C_INCLUDE_DEV_PENCODER = 0 PARAMETER C_DEV_MIR_ENABLE = 0 PARAMETER C_DEV_BLK_ID = 6 PARAMETER C_INCLUDE_INTR_A_BUF = 1 PARAMETER C_INCLUDE_REQ_N_BUF = 1 PARAMETER C_IPIFBAR_NUM = 1 PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000 PARAMETER C_IPIF_SPACETYPE_1 = 0 PARAMETER C_IPIFBAR2PCIBAR_0 = 0x20000000 PARAMETER C_IPIFBAR_0 = 0x20000000 PARAMETER C_IPIF_HIGHADDR_0 = 0x3fffffff PARAMETER C_IPIFBAR_1 = 0xe8000000 PARAMETER C_IPIF_HIGHADDR_1 = 0xebffffff PARAMETER C_BASEADDR = 0x42600000 PARAMETER C_HIGHADDR = 0x4260ffff PARAMETER C_DMA_BASEADDR = 0x42800000 PARAMETER C_DMA_HIGHADDR = 0x4280ffff PARAMETER C_INCLUDE_OPB_MST2PCI_TARG = 0 PARAMETER C_INCLUDE_PCI_CONFIG = 0 PARAMETER C_DEVICE_ID = 0x1004 PARAMETER C_VENDOR_ID = 0x1004 PARAMETER C_CLASS_CODE = 0x050000 PARAMETER C_REV_ID = 0x01 PARAMETER C_SUBSYSTEM_ID = 0xDCBA PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x9876 PARAMETER C_INCLUDE_DEV_ISC = 0 PARAMETER C_INCLUDE_ERR_REG_MODULE = 0 PARAMETER C_IPIF2PCI_FIFO_ABUS_WIDTH = 6 PARAMETER C_PCI2IPIF_FIFO_ABUS_WIDTH = 6 BUS_INTERFACE MSOPB = mb_opb PORT PAR = fpga_0_PCI_Bridge_PAR PORT PERR_N = fpga_0_PCI_Bridge_PERR_N PORT SERR_N = fpga_0_PCI_Bridge_SERR_N PORT IRDY_N = fpga_0_PCI_Bridge_IRDY_N PORT FRAME_N = fpga_0_PCI_Bridge_FRAME_N PORT DEVSEL_N = fpga_0_PCI_Bridge_DEVSEL_N PORT STOP_N = fpga_0_PCI_Bridge_STOP_N PORT TRDY_N = fpga_0_PCI_Bridge_TRDY_N PORT AD = fpga_0_PCI_Bridge_AD PORT CBE = fpga_0_PCI_Bridge_CBE PORT PCLK = pci_feedback_s PORT RST_N = sys_rst_s END
BEGIN dcm_module PARAMETER INSTANCE = dcm_0 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLKFX_BUF = TRUE PARAMETER C_CLKFX_DIVIDE = 6 PARAMETER C_CLKFX_MULTIPLY = 5 PARAMETER C_CLKIN_PERIOD = 25.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_DFS_FREQUENCY_MODE = LOW PARAMETER C_DLL_FREQUENCY_MODE = LOW PARAMETER C_EXT_RESET_HIGH = 1 PORT CLKIN = dcm_clk_s PORT CLK0 = sys_clk_s PORT CLKFX = pci_clk_s PORT CLKFB = sys_clk_s PORT RST = net_gnd PORT LOCKED = dcm_0_lock END