Latest threads in Field-Programmable Gate Arrays

Is there a reset signal available in verilog in Xilinx FPGAs?

As a sample here is some code. To be clear: I am not looking for alternate ways to code the following always block; I w...

2 19yrs

janbeck

2 19yrs janbeck

Placement error for adjacent pins

I have two pin one is IN and the other is INOUT and they each one goes to the D input of two FFs clocked by two differe...

4 19yrs

mhs000

4 19yrs mhs000

Killed a Stratix-II Nios II Altera devkit, How to repair?

Hello, to due a unfortunate chain of events, the cooler of the ep2s60 dropped to the right side of the chip and short-c...

3 19yrs

bfroemel

3 19yrs bfroemel

constraints for design-generated clock

Hi, I am designing a memory controller for a Micron CellularRam and would like to ask what is the best way to generate...

0 19yrs

gyelod

0 19yrs gyelod

Problem cascading 2 DCMs

Hi everyone, I have a problem that is bugging me for 2 days now and I was hoping someone here might be able to help me...

21 19yrs

Michael.Niegl

21 19yrs Michael.Niegl

chip to chip high speed interconnet bus

Hi,everyone,now i want to know how can i change the high speed data between 2 chips=A3=A8one from lattice scm and one f...

0 19yrs

bjzhangwn

0 19yrs bjzhangwn

a question about DDFS

Hi, I am implementing a direct digital frequency synthesizer in FPGA. It follows the equation Fo = N * Fs / (2^M) The i...

2 19yrs

fpga002006

2 19yrs fpga002006

Prope timing constraint for this pin?

Hi. I'm working on a V4 project, but I struggle with the timing constraints. The design has one 125MHz oscillator. In a...

0 19yrs

jetmarc

0 19yrs jetmarc

one extra slipway board from fccm

Hey all, I still have one more slipway board left over to give away; email me if you want it and I'll mail it to you. I...

3 19yrs

megacz

3 19yrs megacz

N00b question about DCM

I have a Spartan3E Starter Kit, and I am trying to figure out how to use the DCM to double the freq from 50MHz to 100MH...

2 19yrs

bob3635x

2 19yrs bob3635x

Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?

2 19yrs

kulkarku

2 19yrs kulkarku

Quartus Fitter Seed Setting

Hello, can anyone comment on setting the "Seed" value in the Fitter group under Setting? How does increasing the value p...

2 19yrs

jjlindula

2 19yrs jjlindula

memory interface for DDR/DDR2 with xilinx spartan 3E/3A starter kits

Hi groups, Hi Xilinx folks, For edu., I am doing some test with DRAM access with xilinx starter kit (3E/3A). I use xili...

0 19yrs

rponsard

0 19yrs rponsard

Question about the simulation library in Xilinx EDK

When I used the EDK simulation library wizard, it never succeeded. So I have to compile the ISE libaray manually under...

0 19yrs

pang.dudu.pang

0 19yrs pang.dudu.pang

Question about the simulation library in EDK

When I used the EDK simulation library wizard, it never succeeded. So I have to compile the ISE libaray manually under...

6 19yrs

pang.dudu.pang

6 19yrs pang.dudu.pang

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