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Placement error for adjacent pins

I have two pin one is IN and the other is INOUT and they each one goes to the D input of two FFs clocked by two different clocks Clk1, Clk2. When I start the PAR process, Xilinx tool complains with the following error:

ERROR:Place:17 - The placement constraints of the IOBs sck and sdi makes this design unroutable due to a physical routing limitation. This device has a shared routing resource connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction means that these pairs of pins must be driven by the same signal or one of the signals will be unroutable. Before continuing please remove the placement constraints or move one of these IOBs to a new location.

The strange thing is that after looking at the design in the FPGA editor, IOBs OTCLK are not used at all in the mentioned IOBs and for one of the pins, the tool is using the internal FFs in the IOB while in the other it's using only an input buffer and that feeds a FF in another slice.

Ofcourse removing the pin placement constraint fixes the problem but that is something that cannot be done for the time being.

I wonder if somebody can help me figure out what's going on.

I'm using ISE 9.1.03i with Spartan 3

Thank you.

Reply to
M. Hamed
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You can't change the architecture of the chip. I ran into this same problem in Virtex 2. Each IOB seems to have two clock inputs that go to the two clocks of the DDR input and output flip-flops, and even if you use the same clock for both (rising edge and falling edge of the same wire) both routing resources are used (wires from the global routing to the IOB. You have to dig a bit deep in the datasheet to find it, but pairs of IOB's (the same pairs labeled as "N" and "P" halves of a differential pair) share only two wires to bring in these two clocks. If both IOB's are using only single data rate flip-flops, the two wires allow them to be pretty much independent of eachother. However when at least one has DDR flip-flops, the two IOB's need to share clock routing. Thus in a DDR SDRAM design for example you can't place a DQ pin and a DQS pin in two halves of a differential pair.

The synthesis tool has apparently worked around this issue in your case by using fabric flip-flops for one of the two IOB's. If you can't change the pin location in your current design, the best you can do is to LOC the fabric slice where these flip-flops will end up. In the package pin listings from Xilinx there is a column showing the location of the nearest (from a routing perspective) slice to each IOB.

HTH, Gabor

PS read the section in the datasheet (ds099) titled "Double-Data-Rate Transmission" in the IOBs functional description. This is p. 13 in my copy which may not be the latest version. The paragraph starting "Some adjacent I/O blocks . . ." describes this.

Reply to
Gabor

The puzzling thing is that I'm not using DDR. The datasheet says "Some adjacent I/O blocks (IOBs) share common routing connecting the ICLK1, ICLK2, OTCLK1, and OTCLK2 clock inputs of both IOBs." It doesn't say which is connected to which. So even though i'm not using DDR, if ICLK1 of IOB1 is connected to ICLK1 of IOB2 and similarly for ICLK2 then there's no problem as long as ICLK1 and ICLK2 of each can function independently and OTCLK are not used at all.

It's puzzling too because as I mentioned, If I remove the constraint and look at the result, the relocated IOB has no ICLK inputs used, only a buffer and then goes to two independent FFs placed somewhere else. So why can't it do that with the constraint in place?

I'll try the LOC suggestion. Thanks for the explanation and suggestions.

/MHS

Reply to
M. Hamed

Afaik each IOB pair in a Spartan 3 has one clock input and a clock enable (or something like that). Bottom line is, you can use one clock in an IOB pair.

This is definitely not mentioned in the Spartan 3 datasheet.

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Reply to
Nico Coesel

from ds099.pdf:

Some adjacent I/O blocks (IOBs) share common routing connecting the ICLK1, ICLK2, OTCLK1, and OTCLK2 clock inputs of both IOBs. These IOB pairs are identified by their differential pair names IO_LxxN_# and IO_LxxP_#, where "xx" is an I/O pair number and '#' is an I/O bank number. Two adjacent IOBs containing DDR registers must share common clock inputs, otherwise one or more of the clock signals will be unroutable.

Reply to
Gabor

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