Field-Programmable Gate Arrays

pcis3base, cesys

Hello Group, i am working on a project with a cesys card (PCIS3BASE). My problem is as follows: I wish to run the basic...

0 comments posted 19yrs

posted by zoshi.s

0 comments posted 19yrs posted by zoshi.s

Need help: Altera ALTPLL_RECONFIG state machine construction

I've asked for help once before on this topic and was directed to look at Ap Note #367. Unfortunately, when I unzip the...

1 comments posted 19yrs

posted by rjmyers

1 comments posted 19yrs posted by rjmyers

WebPACK 9.1i still makes errors with synthesis of BRAMS

Hello all, This is a repeat from article 111605 from November 6-th to this group, see http://www.fpga-faq.com/archives/...

1 comments posted 19yrs

posted by user

1 comments posted 19yrs posted by user

Is microblaze able to change heap_size?

Hi, I have written in this chat a pair of threads about Sdram and heap_size. I want to say that I think that heap_size...

6 comments posted 19yrs

posted by pbantunez

6 comments posted 19yrs posted by pbantunez

How to configure SPI FLASH using Spartan-3E?

I have a system with a Spartan-3E with an SPI flash. I have been using the xspi.exe DOS program to configure the SPI fl...

3 comments posted 19yrs

posted by sven

3 comments posted 19yrs posted by sven

Altera Quartus II v7.0 under openSUSE 10.2

The Altera Quartus II 7.0 software is officially only supported under Red Hat Linux Enterprise 3 and 4 and SUSE Linux E...

1 comments posted 19yrs

posted by n07W17+mgk25

1 comments posted 19yrs posted by n07W17+mgk25

How to drop a Ethernet Packet in Xilinx EMAC

Hi, I am using a Xilinx Ethernet MAC core on the OPB Bus. I would like to know how to drop an ethernet packet. I read t...

1 comments posted 19yrs

posted by get2venu

1 comments posted 19yrs posted by get2venu

Timing constraints with asynchronous clocks

I need help solving a timing problem. I have two clocks one a fast one and a slower one, fclk and sclk. I use two flip...

2 comments posted 19yrs

posted by mhs000

2 comments posted 19yrs posted by mhs000

Modelsim simulation progress in batch/command line mode?

Is there a way I can get ModelSim to display the time progress of the simulation when it's running in command line/batch...

5 comments posted 19yrs

posted by mhs000

5 comments posted 19yrs posted by mhs000

interrupt handler on the Xilkernel PPC405

hallo, people, I am a beginner on Xilkernel running on PPC405-Virtex 4. I just want to get interrupt generated from the...

4 comments posted 19yrs

posted by joy95075

4 comments posted 19yrs posted by joy95075

Memory Resource in SDRAM

Hello, my question is the following: I have created an application created in SDRAM in which I do "xil_malloc(16*4096)"...

0 comments posted 19yrs

posted by pantgom

0 comments posted 19yrs posted by pantgom

Problem with writing values to SRAM from XMD

Hello! I am using a board with Virtex4 PPC405, external asynchronous SRAM memory and EDK 8.2i. If application program r...

2 comments posted 19yrs

posted by plyaskin

2 comments posted 19yrs posted by plyaskin

Increase Memory Resource in SDRAM.

Hi, I have a project with a big requeriment of memory. So I have decided to generate a linker script with every section...

5 comments posted 19yrs

posted by pbantunez

5 comments posted 19yrs posted by pbantunez

OPB master and slave interface for DDR SDRAM controller

Hi, I am almost new in google gruops. I build IPIF master to control OPB DDR SDRAM controller. Using Create/Import Peri...

0 comments posted 19yrs

posted by shineby

0 comments posted 19yrs posted by shineby

Using OPB PCI In EDK 8.1

(This is my third attempt to send the same post to the group. The previous two posts still have not appeared on the gro...

0 comments posted 19yrs

posted by sheikh.m.farhan

0 comments posted 19yrs posted by sheikh.m.farhan