Latest threads in Field-Programmable Gate Arrays

'EVENT (or rising_edge) static prefix requirement....

Can't figure it out... Why cant this compile: S_chan0_clk : process (reset_delayed, ch_clk_div_int) begin for k in 0 to...

5 19yrs

pauljbennett

5 19yrs pauljbennett

XILINX ISE 9.1i: DELAYCHAIN by input data

Hi, I am working on an DSP, have problem by data receiving. As listed below, xilinx ise tools build a "DELAYCHAIN" into...

0 19yrs

uvbaz

0 19yrs uvbaz

About memory interface generater 007 tool

Hi everyone! When I use memory interface generater tool, I select device XC3S400. The tool dosen't generate verilog code...

1 19yrs

gordonfreeman1983

1 19yrs gordonfreeman1983

ISE : Linux - coregen, compxlib errors

Hi I have installed ISE 8.2i on a AMD64 Linux machine running Ubuntu 7.04. ISE works fine, and Ican generate cores, HDL...

1 19yrs

ashwinks

1 19yrs ashwinks

SelectMap or serial: How does the PROM know?

Hello, I am in the midst of reviewing a board design, which is based upon a (Xilinx) Virtex-4 XC4VSX35 which will confi...

5 19yrs

eli.billauer

5 19yrs eli.billauer

ML405 LCD

How can I display "hello world" onto the Char LCD which is on the development board (ML405)? I realized a similar topic...

2 19yrs

c.kevin.lam

2 19yrs c.kevin.lam

Xilinx VHDL Attribute syntax error

Hello, I was switching UCF lines to VHDL attributes when I came into this syntax error. Can someone suggest what the pr...

2 19yrs

bradsmallridge

2 19yrs bradsmallridge

Chipscope with custom cable?

Hi. I'm debugging an issue with my board. The issue surfaces when several components interact, and I'm not able to repr...

4 19yrs

jetmarc

4 19yrs jetmarc

An Open-Source suggestion for Xilinx

An Open-Source suggestion for Xilinx In generic the decision about to use Open-Source strategies is very complex, but t...

29 19yrs

Antti.Lukats

29 19yrs Antti.Lukats

ISE 8.1

Hi there, I'm approaching ISE 8.1i. Trying to Simulate Behaviour Model I get the error message: "HDLParsers:164 - C:/Xi...

0 19yrs

lorenzo.verardo

0 19yrs lorenzo.verardo

Altera FIR Compiler with clock enable

Has anyone had problems with Altera FIR Compiler generated cores when using the clock enable signal? Have a look at my...

2 19yrs

Wilhelm.Klink

2 19yrs Wilhelm.Klink

How to add an IP Core to a Quartus project

I am totally new to all this, so please forgive my naive questions. I have a quartus project that runs on a development...

0 19yrs

benn686

0 19yrs benn686

Second Call for papers - ParaFPGA-2007: Parallel Computing with FPGA's

======================================================== CALL FOR PAPERS ParaFPGA-2007 Parallel Computing with FPGA's A...

0 19yrs

parafpga

0 19yrs parafpga

DMA with ipif / user_logic

Hi! For a small project running Linux on a Virtex2pro, I need to write an IP-component, that recive data from portpins...

4 19yrs

werbung5

4 19yrs werbung5

sysace and high capacity CF

Hi All, I'm planning to attach a high capacity compact flash card to my Spartan-3 design. I don't want to use any file...

0 19yrs

zcsizmadia

0 19yrs zcsizmadia

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