Field-Programmable Gate Arrays

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About memory interface generater 007 tool

Hi everyone! When I use memory interface generater tool, I select device XC3S400. The tool dosen't generate verilog code...
1 comments posted 19yrs
posted by gordonfreeman1983
1 comments posted 19yrs posted by gordonfreeman1983

ISE : Linux - coregen, compxlib errors

Hi I have installed ISE 8.2i on a AMD64 Linux machine running Ubuntu 7.04. ISE works fine, and Ican generate cores, HDL...
1 comments posted 19yrs
posted by ashwinks
1 comments posted 19yrs posted by ashwinks

SelectMap or serial: How does the PROM know?

Hello, I am in the midst of reviewing a board design, which is based upon a (Xilinx) Virtex-4 XC4VSX35 which will confi...
5 comments posted 19yrs
posted by eli.billauer
5 comments posted 19yrs posted by eli.billauer

ML405 LCD

How can I display "hello world" onto the Char LCD which is on the development board (ML405)? I realized a similar topic...
2 comments posted 19yrs
posted by c.kevin.lam
2 comments posted 19yrs posted by c.kevin.lam

Xilinx VHDL Attribute syntax error

Hello, I was switching UCF lines to VHDL attributes when I came into this syntax error. Can someone suggest what the pr...
2 comments posted 19yrs
posted by bradsmallridge
2 comments posted 19yrs posted by bradsmallridge

Chipscope with custom cable?

Hi. I'm debugging an issue with my board. The issue surfaces when several components interact, and I'm not able to repr...
4 comments posted 19yrs
posted by jetmarc
4 comments posted 19yrs posted by jetmarc

An Open-Source suggestion for Xilinx

An Open-Source suggestion for Xilinx In generic the decision about to use Open-Source strategies is very complex, but t...
29 comments posted 19yrs
posted by Antti.Lukats
29 comments posted 19yrs posted by Antti.Lukats

ISE 8.1

Hi there, I'm approaching ISE 8.1i. Trying to Simulate Behaviour Model I get the error message: "HDLParsers:164 - C:/Xi...
0 comments posted 19yrs
posted by lorenzo.verardo
0 comments posted 19yrs posted by lorenzo.verardo

Altera FIR Compiler with clock enable

Has anyone had problems with Altera FIR Compiler generated cores when using the clock enable signal? Have a look at my...
2 comments posted 19yrs
posted by Wilhelm.Klink
2 comments posted 19yrs posted by Wilhelm.Klink

How to add an IP Core to a Quartus project

I am totally new to all this, so please forgive my naive questions. I have a quartus project that runs on a development...
0 comments posted 19yrs
posted by benn686
0 comments posted 19yrs posted by benn686

DMA with ipif / user_logic

Hi! For a small project running Linux on a Virtex2pro, I need to write an IP-component, that recive data from portpins...
4 comments posted 19yrs
posted by werbung5
4 comments posted 19yrs posted by werbung5

sysace and high capacity CF

Hi All, I'm planning to attach a high capacity compact flash card to my Spartan-3 design. I don't want to use any file...
0 comments posted 19yrs
posted by zcsizmadia
0 comments posted 19yrs posted by zcsizmadia

License problems with Quartus 7.0 on Linux

I've been trying to use Quartus 7 on Linux (I've tried three different RedHat/Clone distros, FC6, CentOS 5, Scientific...
2 comments posted 19yrs
posted by schvantzkoph
2 comments posted 19yrs posted by schvantzkoph

computing branch metric for viterbi decoder

Hi, Hi, i saw the circuit for computation of branch metric in the following paper ( figure 3 a ), but i cant understand...
0 comments posted 19yrs
posted by engr.saqib.riaz
0 comments posted 19yrs posted by engr.saqib.riaz