When i add these 2 constraint to my UCF file: CONFIG POST_CRC = "ENABLE"; CONFIG POST_CRC_SIGNAL = "FRAME_ECC_ONLY";
I get these error messages while doing the timing driven packing phase in the map command.
ERROR:Place:911 - CONFIG POST_CRC = ENABLE is not a valid constraint. ERROR:Place:911 - CONFIG POST_CRC_SIGNAL = FRAME_ECC_ONLY is not a valid constraint.
The ngdbuild phase had 0 warnings and errors so i have no indications what could be the problem.
Thankful for any suggestions.
/Peter
What part are you targetting? Ben
Hello,
im targeting xc5vlx30-2-ff676.
/Peter
Ok, sounds strange that it would give you this error...
That and the UG191 explains exactly what you said.
Could it be something really simple... Have you tried without the speech marks?
Ben
I agree, im really puzzled by this. As you indicated i have followed the guidelines when putting these constraints in the ucf.
I have tried with and without " with no change in the result.
Additional information:
When i run without these constraint i get no errors and i get the FRAME_ECC instanciated correctly. (Verified in FPGA editor.)
Also i use only the CRCERROR output from the primitive when i infer it in the VHDL code.
well, i'm at a loss...
Perhaps it could be worth your while making a _VERY_ small code that only uses these signals with some dumb logic to see if you can narrow it down to a code optimisation, or a bug in the place/route.
Ben
I've reproduced this error. It's a 9.1i SP2 regression. Earlier versions work. I'll file a CR.
Bret (Xilinx Product Applications)
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