Assuminng that you can get more bandwidth out of the fiber than the DVI, you should be able to do it without any external RAM, and using only a very small amount of RAM in the FPGA for FIFO buffering.
Design one block that receives the data from DVI into a FIFO, and a second that pulss data from the FIFO and transmits it on the fiber. When the FIFO is empty (or low), send a fill pattern on the fiber.
At the receiving end, non-fill data from the fiber goes into a FIFO.
There's a potential problem with rate mismatch between your DVI clocks at the two ends. If the transmitter derives the fiber clock frequency from the DVI using a PLL or DLL, the receivinng end can derive the DVI frequency from the fiber frequency, avoiding the problem.
Hello, i designed such a thing with an FPGA in our entire products. We have a ready design running up to 1920x1200@24 RGB with Analog or DVI-Input and local loopback. Due to the limit of the 2.5 Gbits, we can only support Framerates about
30 FPS@24 Bit colourdepht over the Fibre (when you reduce colourdepth the framerate can be higher). The framerate will then be restored with an Framebuffercontorller on the RX to 60Hz. In further releases we want to feature things like losless compressions to enable higher refresh rates over the fibre. If you are interessted in our product, design support or other things, don't hesitate to contact me via mail.
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