ISE 9.1 Hierarchy Problem

I recently switched over to ISE 9.1 and I noticed a problem where ISE won't recognize the design hierarchy. Thinking that it might be something specific to my design, I tried the example design files provided with one of the Xilinx cores and lo and behold the design hierarchy is incorrect again.

Eventually I figured out that it is the synthesis directives (e.g. "// synthesis syn_noclockbuf = 1") that seem to cause this problem. When I remove the synthesis directives, ISE 9.1 recognizes the hierarchy correctly. This behavior is repeatable:

1. When I remove the synthesis directives, the hierarchy appears correctly.
2. When I include the synthesis directives, the hierarchy disappears.

Has anyone else noticed something similar or have any insight into fixing this problem?