Latest threads in Field-Programmable Gate Arrays

Power Consumption near Timing Failure Point

I know that an FPGA's power consumption is basically linear with clock frequency, but does anybody know what happens wh...

12 19yrs

kevin_neilson

12 19yrs kevin_neilson

Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards

Hello, I am graduate student in the Dept. of Computer Sc. & Engg. in USF. We are using a Digilent XUP2vpPro board for o...

7 19yrs

koustav79

7 19yrs koustav79

Designer

Good evening guys and gals, my name is Mark and I am a technical recruiter in Mclean, VA. I am sorry to bother all of y...

2 19yrs

markwaddell

2 19yrs markwaddell

LF VHDL to FSM bubble diagram translator

Hi all, I was wondering if there is such a thing available? I found a few free and commercial tools to edit/create bubb...

3 19yrs

mbmsv

3 19yrs mbmsv

ise project navigator can't dereference edk pcores from XilinxProcessorIPLib

First of all. Thanks for the bus macro advise. The second problem still remains. After creating a system with base syst...

4 19yrs

l.s.rockfan

4 19yrs l.s.rockfan

Using dynamic reconfiguration ports of DCMs on Virtex 4

Hello, I've been reading the posts in this forum for a long time. This is my first time asking a question here. I'm wor...

0 19yrs

emotuk

0 19yrs emotuk

Xilinx SD-RAM-Controller (Xilinx EDK 8.2)--problems with xil_printf reading from memory

Hello, I've some problems with reading from my sd-ram. On my FPGA is a Xilinx Virtex 2 XC2V1000 chip and I want to use...

3 19yrs

rmeiche

3 19yrs rmeiche

debit- xilinx bitstream decompiler project has been vanished? or does someone know the URL

good thing do not seem to be long online, the bitstream decompiler project seems not available, at least I can find the...

0 19yrs

Antti.Lukats

0 19yrs Antti.Lukats

How low DDR2 Clock Frequency can be? To make it work on FPGA.

Hello, I have a DDR2 Controller ASIC rtl, which i need to put on FPGA and validate it. The problem is, i am not able to...

14 19yrs

amit3007

14 19yrs amit3007

Xilinx ISE 9.1 Simulator does not work with glibc 2.5

Hi List, I cannot run the ISE-Simulator on a Gentoo Laptop with glibc 2.5. The simulation seems to run fine, but the Si...

2 19yrs

tmueller

2 19yrs tmueller

coregen -> simulation error in modelsim

When i try to simulate a coregen generated single port ram, i get a error from modelsim : # -- Loading package blkmemsp...

3 19yrs

kislo02

3 19yrs kislo02

Xilinx EDK: Slow OPB write speeds

Hi All, I've a simple peripheral with an OPB interface. In a nutshell I've been getting some very slow write speeds ove...

10 19yrs

ajg112

10 19yrs ajg112

reading IDCODE from parallel bus?

Is there any way to read IDCODE (and execute other jtag commands) using the parallel config bus? I can't find any inform...

2 19yrs

mleikvol

2 19yrs mleikvol

bus macros for partial reconfiguration of virtex2pro?

Hi everybody. I'm sitting over a partial reconfiguration project for university. I'm absolutelly new to this topic, but...

1 19yrs

l.s.rockfan

1 19yrs l.s.rockfan

Timing constraint question

Hello, I am trying to specify a timing constraint for a latch that I have in my design. I need to make sure that from t...

8 19yrs

Dmitriy.Bekker

8 19yrs Dmitriy.Bekker

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