Field-Programmable Gate Arrays

Designer

Good evening guys and gals, my name is Mark and I am a technical recruiter in Mclean, VA. I am sorry to bother all of y...

2 comments posted 19yrs

posted by markwaddell

2 comments posted 19yrs posted by markwaddell

LF VHDL to FSM bubble diagram translator

Hi all, I was wondering if there is such a thing available? I found a few free and commercial tools to edit/create bubb...

3 comments posted 19yrs

posted by mbmsv

3 comments posted 19yrs posted by mbmsv

ise project navigator can't dereference edk pcores from XilinxProcessorIPLib

First of all. Thanks for the bus macro advise. The second problem still remains. After creating a system with base syst...

4 comments posted 19yrs

posted by l.s.rockfan

4 comments posted 19yrs posted by l.s.rockfan

Using dynamic reconfiguration ports of DCMs on Virtex 4

Hello, I've been reading the posts in this forum for a long time. This is my first time asking a question here. I'm wor...

0 comments posted 19yrs

posted by emotuk

0 comments posted 19yrs posted by emotuk

Xilinx SD-RAM-Controller (Xilinx EDK 8.2)--problems with xil_printf reading from memory

Hello, I've some problems with reading from my sd-ram. On my FPGA is a Xilinx Virtex 2 XC2V1000 chip and I want to use...

3 comments posted 19yrs

posted by rmeiche

3 comments posted 19yrs posted by rmeiche

debit- xilinx bitstream decompiler project has been vanished? or does someone know the URL

good thing do not seem to be long online, the bitstream decompiler project seems not available, at least I can find the...

0 comments posted 19yrs

posted by Antti.Lukats

0 comments posted 19yrs posted by Antti.Lukats

How low DDR2 Clock Frequency can be? To make it work on FPGA.

Hello, I have a DDR2 Controller ASIC rtl, which i need to put on FPGA and validate it. The problem is, i am not able to...

14 comments posted 19yrs

posted by amit3007

14 comments posted 19yrs posted by amit3007

Xilinx ISE 9.1 Simulator does not work with glibc 2.5

Hi List, I cannot run the ISE-Simulator on a Gentoo Laptop with glibc 2.5. The simulation seems to run fine, but the Si...

2 comments posted 19yrs

posted by tmueller

2 comments posted 19yrs posted by tmueller

coregen -> simulation error in modelsim

When i try to simulate a coregen generated single port ram, i get a error from modelsim : # -- Loading package blkmemsp...

3 comments posted 19yrs

posted by kislo02

3 comments posted 19yrs posted by kislo02

Xilinx EDK: Slow OPB write speeds

Hi All, I've a simple peripheral with an OPB interface. In a nutshell I've been getting some very slow write speeds ove...

10 comments posted 19yrs

posted by ajg112

10 comments posted 19yrs posted by ajg112

reading IDCODE from parallel bus?

Is there any way to read IDCODE (and execute other jtag commands) using the parallel config bus? I can't find any inform...

2 comments posted 19yrs

posted by mleikvol

2 comments posted 19yrs posted by mleikvol

bus macros for partial reconfiguration of virtex2pro?

Hi everybody. I'm sitting over a partial reconfiguration project for university. I'm absolutelly new to this topic, but...

1 comments posted 19yrs

posted by l.s.rockfan

1 comments posted 19yrs posted by l.s.rockfan

Timing constraint question

Hello, I am trying to specify a timing constraint for a latch that I have in my design. I need to make sure that from t...

8 comments posted 19yrs

posted by Dmitriy.Bekker

8 comments posted 19yrs posted by Dmitriy.Bekker

Lockup with Xilinx mch_opb_ddr

Hi, I'm using the mch_opb_ddr-controller V1.00c from EDK8.2 in a Microblaze design. Beside the Microblaze, another bus...

2 comments posted 19yrs

posted by acher

2 comments posted 19yrs posted by acher

does SRL exist in non-xilinx FPGAs?

Hey, Is there any non-xilinx FPGA that has the equivalent of Xilinx Virtex SRL component as a basic component logic? If...

1 comments posted 19yrs

posted by tlenomade

1 comments posted 19yrs posted by tlenomade